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fix the bug of global barrier and add the tests that can reproduce the previous bug. - #412

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symmetryyyyy wants to merge 4 commits into
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review/gbar-response-phase-20260903
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fix the bug of global barrier and add the tests that can reproduce the previous bug.#412
symmetryyyyy wants to merge 4 commits into
masterfrom
review/gbar-response-phase-20260903

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@symmetryyyyy

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1 Add a regression test to reproduce the previous bug: introduce gbar_phase, a two-core SimX/RTLSim test that reproduces the global-barrier response-phase bug and verifies phase advancement across completed generations.
2 Enhance asynchronous stress coverage: extend the split arrive/wait loop in async_gbarrier from 32 to 1024 iterations, making delayed responses and phase reuse observable.
3 Restructure global-barrier response handling: replace the single pending-request state with per-barrier pending/phase/waiter bookkeeping and a request FIFO, so responses are matched by barrier ID and routed to the correct phase and waiting warps.

symmetryyyyy and others added 4 commits September 2, 2026 16:09
Add non-deadlocking diagnostics for cross-slot local phase corruption and missing global-barrier phase advancement. Register both tests in the aggregate regression suite and explicit SimX/xrtsim smoke coverage.

Co-Authored-By: RunjiaChen <runjia@u.nus.edu>

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Capture the phase and exact waiters for each pending global-barrier generation, queue completed local arrivals, and route each cluster response directly to its barrier slot. Keep response-only writes out of the barrier state RAM and qualify the working phase bypass by address.

Use one-bit phase toggles in SimX so wait comparisons keep matching the RTL after wraparound.
@tinebp

tinebp commented Sep 10, 2026

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Closing as superseded by #407.

Both PRs carry the identical three commits — `451dded2a`, `3b5b6f7bc`, `9e5f577e2` — and the RTL and SimX changes are byte-for-byte identical (`git diff pr/407 pr/412` on `hw/rtl/core/VX_bar_unit.sv`, `sim/simx/barrier_unit.cpp` and `tests/regression/async_gbarrier` is empty). The differences are the base commit and the fourth commit here, bc90d020c, which unregisters bar_slot_phase and moves gbar_phase from the xrt leg to rtlsim.

#407 is the one being kept because it registers both reproducers, and bar_slot_phase is a real RTL failure that this fix repairs. Verified locally on a clean worktree at origin/master (bf1831ca3), 2 cores:

test driver clean master with the fix
bar_slot_phase (256 rounds) simx PASS PASS
bar_slot_phase rtlsim FAIL — 512 errors PASS — 0 errors
gbar_phase simx PASS PASS
gbar_phase rtlsim FAIL — 0 -> 0 PASS — 0 errors
async_gbarrier (widened 32 -> 1024) rtlsim PASS

Landing this PR instead would put the fix for #401 on master with nothing in CI guarding it.

On the xrt -> rtlsim change: both spellings pass ci/testcase.py lint, so it is not a policy violation, but the existing multi-core global-barrier coverage on master is dogfood-1 on simx and dogfood-2 on xrt at cores: 2, and 78f15e80d is what deliberately moved the multi-core gbar dogfood to xrt. #407 follows that pattern. Since xrtsim's coverage strictly contains rtlsim's, the xrt leg also exercises the AFU and driver path for the same case.

No work is lost — every commit here is in #407.

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