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ASIC Gate ASIC Gate #10: Scheduled
4m 23s master
master
4m 23s
FPGA Gate FPGA Gate #15: Scheduled
4h 42m 33s master
master
4h 42m 33s
ASIC Gate ASIC Gate #9: Scheduled
4m 7s master
master
4m 7s
FPGA Gate FPGA Gate #14: Scheduled
4h 54m 22s master
master
4h 54m 22s
vm: banked L1 TLB and a device-level shared page-table walker CI #1818: Pull request #406 synchronize by tinebp
14h 59m 59s ATWeatherly:vm-arch-master
ATWeatherly:vm-arch-master
14h 59m 59s
Fix barrier phase routing and global response tracking (#407) CI #1817: Commit 1cd71c4 pushed by tinebp
17h 55m 6s master
master
17h 55m 6s
diverge: rename NV_ITS->ITS, ITS scheduler timing redesign, SCS vx_sb… CI #1816: Commit 8b20ebe pushed by tinebp
15h 12m 0s threadsplit
threadsplit
15h 12m 0s
ASIC Gate ASIC Gate #8: Scheduled
4h 36m 6s master
master
4h 36m 6s
Fix barrier phase routing and global response tracking CI #1815: Pull request #407 synchronize by tinebp
16h 23m 24s fix/gbar-response-phase
fix/gbar-response-phase
16h 23m 24s
Merge branch 'master' into fix/gbar-response-phase CI #1814: Commit 4e2f0c8 pushed by tinebp
16h 28m 17s fix/gbar-response-phase
fix/gbar-response-phase
16h 28m 17s
tests/unittest: cover reserved RVC code points CI #1813: Commit bf1831c pushed by tinebp
19h 41m 53s master
master
19h 41m 53s
FPGA Gate FPGA Gate #13: Scheduled
5h 59m 21s master
master
5h 59m 21s
simx: reject RV32 shift-immediate code points with shamt[5] set CI #1812: Commit 1303434 pushed by tinebp
6h 43m 49s master
master
6h 43m 49s
diverge: SCS fused loop-branch vx_pbr + NV_ITS regroup pipeline split CI #1811: Commit a22343e pushed by tinebp
5h 2m 19s threadsplit
threadsplit
5h 2m 19s
diverge: adopt SCS/ThreadSplit terminology and unify the yield flag CI #1810: Commit fcbac91 pushed by tinebp
6h 53m 35s threadsplit
threadsplit
6h 53m 35s
diverge: adopt SCS/ThreadSplit terminology and unify the yield flag Apptainer CI #101: Commit fcbac91 pushed by tinebp
57m 49s threadsplit
threadsplit
57m 49s
FPGA Gate FPGA Gate #12: Manually run by tinebp
5h 51m 49s master
master
5h 51m 49s
Apptainer CI Apptainer CI #100: Scheduled
6h 30m 12s master
master
6h 30m 12s
ASIC Gate ASIC Gate #7: Scheduled
8h 49m 8s master
master
8h 49m 8s
FPGA Gate FPGA Gate #11: Scheduled
9h 35m 36s master
master
9h 35m 36s
vm: banked L1 TLB and a device-level shared page-table walker CI #1809: Pull request #406 synchronize by tinebp
10h 43m 22s ATWeatherly:vm-arch-master
ATWeatherly:vm-arch-master
10h 43m 22s
tests: vm_stress — TLB pressure mixed with a VX_MEM_PHYS identity-map… CI #1808: Commit 451e048 pushed by tinebp
9h 28m 10s master
master
9h 28m 10s
vm_stress — TLB pressure mixed with an identity-mapped physical buffer CI #1807: Pull request #405 synchronize by tinebp
9h 33m 7s ATWeatherly:vm-stress-master
ATWeatherly:vm-stress-master
9h 33m 7s
docs: add timelines from latest S2G traces CI #1806: Commit b1593b3 pushed by symmetryyyyy
17h 30m 1s review/s2g-simple-groups-20260908
review/s2g-simple-groups-20260908
17h 30m 1s
dxa: simplify per-warp S2G groups and fixed dispatch CI #1805: Commit 0437db3 pushed by symmetryyyyy
11h 24m 33s review/s2g-simple-groups-20260908
review/s2g-simple-groups-20260908
11h 24m 33s