fix(reset): coordinate V80 SBR with PCIe hotplug

[amd-vserbu]

Summary

Make a V80 secondary-bus reset one serialized operation that suppresses reset-induced PCIe hotplug events, waits for PDI reload and stable link training, and returns control only when userspace can safely rescan and reopen all three functions.

Reset race

A V80 SBR triggers a full PDI reload rather than only retraining an ordinary endpoint link. The existing path releases PCI topology serialization before reset and relies on fixed sleeps. During that interval, pciehp can interpret the expected link transitions as physical removal events, while userspace may rescan before PF0, PF1, PF2, their drivers, and udev permissions are ready.

The reset contract also permits callers to leave functions on the secondary bus, which makes it possible to reset underneath live driver state.

Changes

The hotplug ioctl now requires an empty secondary bus and holds pci_lock_rescan_remove() through reset and link recovery. On a hotplug-capable bridge it temporarily sets the legacy ignore_hotplug flag, performs pci_bridge_secondary_bus_reset(), allows five seconds for the V80 PDI reload, and then requires DLL Link Active to remain asserted across two 100 ms polls. The ioctl times out after a further 25 seconds and restores the previous hotplug state on every exit path.

Holding the global PCI rescan/remove lock can block unrelated PCI topology changes for up to 30 seconds. This is deliberate: the V80 must remain one atomic topology transition, and supported kernels do not export the newer PCI hotplug coordination helper to this out-of-tree module.

After the ioctl succeeds, vrtd rescans immediately instead of adding another fixed post-SBR sleep. It polls every 100 ms for PF0 AMI readiness and accessible PF1 QDMA and PF2 control nodes, retaining the AMI handle while udev finishes the remaining nodes. A rescan that does not produce all three functions within ten seconds is retried up to five times.

Draft

Needs rebase and testing