wallace-tree

Here are 4 public repositories matching this topic...

KARAN-D05 / Gate-Level-Cybernetic-Classifier

This project explores how adaptive behavior and learning-like dynamics can emerge from purely deterministic gate-level systems. It evolves from strict Boolean matching to score-based decision making, culminating in a cybernetic feedback-driven adaptive learning system 🤖.

verilog finite-state-machine adaptive-learning pattern-recognition cybernetics icarus-verilog gtkwave learning-algorithms yosys artificial-neuron digital-system-design hardware-optimization logisim-evolution algorithmic-optimization threshold-based-decision-making wallace-tree self-learning-system speed-vs-area-tradeoffs

Updated Aug 20, 2026
Verilog

KMnO4-158 / multiplied

Star

A powerful tool to build, test, and analyse multiplier designs.

python dadda-tree binary-multiplier wallace-tree

Updated Apr 5, 2026
Python

Faraz-shaikh-9 / Wallace-Tree-Multiplier-Verilog

Star

4x4 Wallace Tree Multiplier using Carry Save Adder (CSA) and Carry Lookahead Adder (CLA) in Verilog HDL.

asic fpga gtkwave vlsi iverilog multiplier rtl-design hardware-design wallace-tree

Updated Jun 22, 2026
Verilog

Sarkar22 / sv-arith

Star

Parametric structural adders and multipliers in SystemVerilog: unsigned, signed (Baugh-Wooley and radix-4 Booth) and floating point (FP8 e4m3/e5m2, bf16, fp16), verified exhaustively and placed and routed on sky130 (41-design area-delay sweep)

Updated Sep 20, 2026
SystemVerilog

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