single-cycle

Verilog Implementation of an ARM LEGv8 CPU

LEGv8 CPU implementation and some tools like a LEGv8 assembler

Single Cycle 32 bit MIPS

VHDL implementation of a 1 Hz single cycle CPU that supports recursive function calls

Single-Cycle CPU for Homework of Computer System Design in CUMT.

Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.

A single cycle CPU running MIPS instructions on Xilinx FPGA

MIPS CPU constructed in verilog

Simple RISC-V CPUs running a baremental ray-tracer program.

simple mips architecture

1052_計算機組織 COMPUTER ORGANIZATION

An implementation of rv32i single cycle processor on logisim

RV32I Single Cycle Processor in Verilog — ASIC tapeout with Genus & Innovus

A simplified single-cycle RISC processor implemented in VHDL for educational computer architecture projects.

Verilog modules covering the single cycle processor

Single-cycle and multi-cycle implementation of a subset of MIPS instruction set

Verilog implementation of Two-Key Triple DES (3DES) with Single-Cycle, Multi-Cycle, and Pipelined architectures supporting ECB, CBC, and OFB modes.

Computer Architecture I (University of Aveiro)

Home work checker for Single-Cycled-Processor

Implementação didática de um processador RISC-V (RV32I) em Logisim, com datapath e unidade de controle construídos apenas com circuitos lógicos digitais.