This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
-
Updated
Jun 6, 2021 - Verilog
#
gate-level-simulation
Here are 15 public repositories matching this topic...
USAGI is a Python script designed to automate the process of synthesizing and performing gate-level simulations for digital designs across a range of cycle times.
-
Updated
Nov 21, 2024 - Python
Gate-Level Simulation on a GPU
-
Updated
Nov 22, 2016 - C++
This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022
image-processing object-oriented systemc object-oriented-programming gate-level system-modeling systemc-ams gate-level-simulation rtl-design
-
Updated
Jul 29, 2022 - C++
A Parallel Discrete Event Simulation Engine with Examples
software-engineering multi-core partitioning metis conservative many-core discrete-event-simulation sychronization logic-simulator des-simulators queueing-networks pdes gate-level-simulation parallel-simulation parallel-discrete-event-simulation
-
Updated
Oct 15, 2022 - C++
Digital Logical Designs Course Projects
-
Updated
Aug 19, 2022 - Verilog
RTL Design and ASIC synthesis workshop using Verilog, Yosys, GTKWave, and SKY130 open-source PDK. Includes RTL simulation, synthesis, Gate-Level Simulation (GLS), optimization techniques, waveform analysis, and synthesis-aware digital design experiments.
open-source verilog synthesis gtkwave vlsi yosys iverilog digital-design gate-level-simulation rtl-design sky130
-
Updated
May 22, 2026
FuzzyACOR-Algorithm (Adaptive fuzzy metaheuristic based optimisation algorithm)
layouts optimization layout ant-colony-optimization fuzzy-logic optimisation optimisation-algorithms gate-level ant-colony-optimisation electronics-design gate-level-simulation flipflop jkflipflop ant-colony-algorithm powerconsumption cmos-circuits adaptive-fuzzy-logic fuzzy-adaptive optimum-layout layout-design
-
Updated
May 10, 2022 - MATLAB
Gate-level implementation of a full-adder using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.
verilog icarus-verilog gtkwave testbench waveform-analysis digital-logic-design full-adder logic-circuits vlsi-design gate-level-simulation
-
Updated
Feb 4, 2025 - Verilog
A battle-tested OpenLane guide covering WSL2, Docker, PDK, OpenLane1/OpenLane2 coexistence, GLS, STA, layout tools, and disaster-proof environment management. Read once, never break your OpenLane setup again.
docker magic asic layout eda vlsi klayout sta pdk physical-design openroad gate-level-simulation wsl2 openlane sky130 gf180 reproducible-builds-eda
-
Updated
Feb 21, 2026 - CSS
Gate-level implementation of a 2-to-1 multiplexer using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.
open-source verilog mux icarus-verilog gtkwave multiplexer testbench waveform-analysis digital-logic-design vlsi-design gate-level-simulation
-
Updated
Feb 5, 2025 - Verilog
Advanced Chemistry Tools for NEET, JEE, CSIR-NET, GATE, IIT-JAM, JEE ADVANCED, BHU, BITSAT, CBSE, State Board Exams: pH Calculator, Salt Hydrolysis, and Titration Simulators."
chemistry neet chemistry-solver jeemain bhu chemistry-lab assistant-professor gate-level-simulation iit-jee chemistry-education jeemains bitsat csir-net gate-notes rpsc-study-material rpsc-preparation chemistry-tool neet-exam csir-net-chemical-science
-
Updated
Mar 6, 2026 - JavaScript
Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)
c assembly spike verilog gtkwave soc yosys risc-v iverilog gate-level-simulation hardware-design chipcron
-
Updated
May 8, 2024 - Verilog
Add this topic to your repo
To associate your repository with the gate-level-simulation topic, visit your repo's landing page and select "manage topics."