Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation including a final report and project progression presentation.
Open-source, agent-agnostic RTL formal verification skill library for AI coding agents: JasperGold FPV, SVA, proof optimization, and TCL workflows for Claude Code, Codex, Gemini CLI, and Cursor.
This project uses UVM to verify an SPI Slave connected to internal RAM. It includes multiple agents (active and passive) and integrates assertion-based verification for both SPI and RAM behavior.
UVM-based verification portfolio for APB, AXI, I2C, SPI, and UART protocols. Class-based testbenches with sequence library, reference model, dual TLM-FIFO scoreboard, functional coverage (uvm_subscriber), SVA assertions, and Makefile/TCL build flow.
UVM-Verified CXL.mem Type 3 Memory Expander Controller. Dynamically bridges high-bandwidth CXL.mem cachelines (512-bit) to AXI4 (32-bit) with concurrent SystemVerilog Assertions (SVA) and functional coverage closure.
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