bench: add memchr vs scalar comparison for #718

[dhimasardinata]

Related to #718, #405

Adds benches/issue718.rs to reproduce scalar vs SIMD gap from memchr_vs_stringzilla table in #718:

	Intel forward	Intel reverse	Arm forward
memchr	5.89 GB/s	1.08 GB/s	6.38
stringzilla	8.37	8.21	6.56

This bench uses existing sample_rss.xml:194K x20 and compares:

• scalar iter.position(|&b| matches!(b, <>&'"\r)) (old _escape)
• SIMD 2x memchr3 (new SIMD accelerated escape routines #405 impl)

Run: cargo bench --bench issue718 -- --sample-size 10

Provides baseline for #405 and future stringzilla/AVX-512 exploration without adding C++ dep. Can extend to stringzilla-rs binding later.

[dralley]

Name the file / bench simd_vs_scalar bench or something, not issue718

[dhimasardinata]

Renamed per review: benches/issue718.rs -> benches/simd_vs_scalar.rs and bench name simd_vs_scalar. Thanks!

[codecov-commenter]

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Codecov Report

❌ Patch coverage is 0% with 56 lines in your changes missing coverage. Please review.
✅ Project coverage is 55.00%. Comparing base (e00ae5c) to head (e76e904).
⚠️ Report is 74 commits behind head on master.

Files with missing lines	Patch %	Lines
benches/simd_vs_scalar.rs	0.00%	56 Missing ⚠️
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Additional details and impacted files

@@            Coverage Diff             @@
##           master    #1014      +/-   ##
==========================================
- Coverage   57.31%   55.00%   -2.32%     
==========================================
  Files          46       52       +6     
  Lines       18197    18847     +650     
==========================================
- Hits        10429    10366      -63     
- Misses       7768     8481     +713     

Flag	Coverage Δ
unittests	55.00% <0.00%> (-2.32%)	⬇️

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