Improve handling of function inlining a bit more - #32
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… when generating some code using target-specific builtins
…o allow recursive types
gcc/config/i386: PR jit/TODO * i386-builtins.cc: New function (clear_builtin_types). gcc/jit: PR jit/TODO * dummy-frontend.cc: Include headers target.h, jit-recording.h, unordered_map and string, new variables (target_function_types, and target_builtins_ctxt), new function (tree_type_to_jit_type). * jit-builtins.cc: Specify that the function types are not from target builtins. * jit-playback.cc: New argument is_target_builtin to new_function. * jit-playback.h * jit-recording.cc * jit-recording.h * libgccjit.cc * libgccjit.h * libgccjit.map gcc/testsuite/jit.dg: PR jit/TODO * all-non-failing-tests.h * test-target-builtins.c
Fix compilation error when bfloat is unsupported
Add test for cold attribute in libgccjit
fixup! WIP: Add support for function attributes
Add ability to get CPU features
Add support for returns_twice attribute in libgccjit
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…26597]
aarch64_expand_vec_perm_const_1 normalizes a permutation whose first index
selects the second operand by rotating the indices and swapping op0 and op1.
It left zero_op0_p and zero_op1_p pointing at the old operands, so the later
recognizers that consult them, aarch64_evpc_and and aarch64_evpc_tbl, read
the wrong vector.
Swap the two flags together with the operands.
For
typedef int v4si __attribute__ ((vector_size (16)));
v4si f (v4si x)
{
const v4si m = { 4, 1, 2, 3 };
return __builtin_shuffle (x, (v4si) { 0, 0, 0, 0 }, m);
}
at -O0 the AND was applied to the all-zero operand, so the function returned
{0,0,0,0} instead of {0,x1,x2,x3}:
sub sp, sp, rust-lang#32
str q0, [sp]
adrp x0, .LC0
add x0, x0, :lo12:.LC0
ldr q31, [x0]
str q31, [sp, 16]
movi v31.4s, 0
fmov s31, s31
mov v0.16b, v31.16b
add sp, sp, 32
ret
With the fix the AND is applied to the incoming vector:
sub sp, sp, rust-lang#32
str q0, [sp]
adrp x0, .LC0
add x0, x0, :lo12:.LC0
ldr q31, [x0]
str q31, [sp, 16]
ldr q30, [sp]
adrp x0, .LC1
add x0, x0, :lo12:.LC1
ldr q31, [x0]
and v31.16b, v30.16b, v31.16b
mov v0.16b, v31.16b
add sp, sp, 32
ret
Bootstrapped and tested on aarch64-none-linux-gnu.
gcc/ChangeLog:
PR target/126597
* config/aarch64/aarch64.cc (aarch64_expand_vec_perm_const_1): Swap
zero_op0_p and zero_op1_p along with the operands.
gcc/testsuite/ChangeLog:
PR target/126597
* gcc.target/aarch64/pr126597.c: New test.
Signed-off-by: Kyrylo Tkachov <ktkachov@nvidia.com>
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