Prepare qcom-next based on tag 'Linux 7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git - #1031
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Add a V4L2 sub-device driver for the Samsung S5KJN5, a 50 MP GBRG 10-bit RAW MIPI CSI-2 image sensor. The driver supports the 4096x3072 mode and exposes the standard controls (exposure, gain, vblank/hblank, test pattern). Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260724-sk5jn5-v2-1-871d3b9a2e47@oss.qualcomm.com/
Add bindings for the Camera Subsystem for X1P42100. The X1P42100 platform provides: - 2 x CSIPHY - 3 x TPG - 3 x CSID - 2 x CSID Lite - 1 x IFE - 2 x IFE Lite Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
The Purwa camera subsystem is a cut-down variant of the Hamoa CAMSS. Compared to Hamoa, Purwa provides only two CSIPHY instances and does not include the VFE1. Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Add three I2C-connected GPIO expanders on Talos Lyra EVK board to provide additional GPIO lines for extended I/O functionality. Signed-off-by: Nirmesh Kumar Singh <nirmesh.singh@oss.qualcomm.com>
…gulator" This reverts commit 32998bb in favour of the upstream fix, which is applied in the following patch. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…CIe PHYs The QMP PCIe PHYs on QCS8300 require dedicated qref and refgen voltage supplies for stable operation. Without these supplies, the system may occasionally crash. Add vdda-qref-supply and vdda-refgen-supply in the board files (QCS8300-RIDE, Monaco-EVK and Monaco-Monza-SoM), and add refgen-supply in the SoC DTSI (monaco.dtsi) since refgen is an on-chip regulator shared across boards. The PHY driver votes for refgen3 directly as a workaround for a hardware issue where QREF actually depends on refgen3 rather than refgen2 as documented. Link: https://lore.kernel.org/all/20260810112735.1326807-4-ziyue.zhang@oss.qualcomm.com/ Fixes: 33967ea ("arm64: dts: qcom: qcs8300-ride: enable pcie0 interface") Fixes: cdb613a ("arm64: dts: qcom: qcs8300-ride: enable pcie1 interface") Fixes: 41e2424 ("arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1.") Fixes: 5238f4e ("arm64: dts: qcom: Add Monaco Monza SoM") Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Add support for RGBIR camera dt node as sensor 14. Signed-off-by: Nirav Khatri <khatri@qti.qualcomm.com>
Add flag "aggregator-rx" to the Hamoa and Purwa camera dtsi. This change enables the aggregated CSIPHY to enable the GMSL Camera and Per-port feature. Signed-off-by: Vishal Verma <vishverm@qti.qualcomm.com>
…ault"" The kaanapali-MTP crash that prompted the workaround was due to frame done timeouts on DSI. That issue is now fixed and frame done timeouts are no longer seen on kaanapali DSI with virtual planes enabled. Virtual planes are also required for 4K display support on Kodiak (SC7280). Re-enable virtual planes by default. This reverts commit 7a17c61. Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
Register optional operation-points-v2 table for ICE device during device probe. Attach the OPP-table with only the ICE core clock. Since, dtbinding is on a transition phase to include iface clock and clock-names, attaching the opp-table to core clock remains optional such that it does not cause probe failures. Introduce clock scaling API qcom_ice_scale_clk which scale ICE core clock based on the target frequency provided and if a valid OPP-table is registered. Use round_ceil passed to decide on the rounding of the clock freq against OPP-table. Clock scaling is disabled when a valid OPP-table is not registered. This ensures when an ICE-device specific OPP table is available, use the PM OPP framework to manage frequency scaling and maintain proper power-domain constraints. Link: https://lore.kernel.org/all/20260824-enable-ice-clock-scaling-v12-1-09271f583dc6@oss.qualcomm.com/ Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Implement ICE (Inline Crypto Engine) clock scaling in sync with UFS controller clock scaling. This ensures that the ICE operates at an appropriate frequency when the UFS clocks are scaled up or down, improving performance and maintaining stability for crypto operations. For scale_up operation ensure to pass ~round_ceil (round_floor) and vice-versa for scale_down operations. In case of OPP scaling is not supported by ICE, ensure to not prevent devfreq for UFS, as ICE OPP-table is optional. Link: https://lore.kernel.org/all/20260824-enable-ice-clock-scaling-v12-2-09271f583dc6@oss.qualcomm.com/ Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Acked-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
MMC controller lacks a clock scaling mechanism, unlike the UFS controller. By default, the MMC controller is set to TURBO mode during probe, but the ICE clock remains at XO frequency, leading to read/write performance degradation on eMMC. To address this, set the ICE clock to TURBO during sdhci_msm_ice_init to align it with the controller clock. This ensures consistent performance and avoids mismatches between the controller and ICE clock frequencies. For platforms where ICE is represented as a separate device, use the OPP framework to vote for TURBO mode, maintaining proper voltage and power domain constraints. Link: https://lore.kernel.org/all/20260824-enable-ice-clock-scaling-v12-3-09271f583dc6@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
… SDHC nodes Qualcomm Inline Crypto Engine (ICE) platform driver now, supports an optional OPP-table. Add OPP-table for ICE UFS and ICE SDHC device nodes for Kodiak platform. Link: https://lore.kernel.org/all/20260824-enable-ice-clock-scaling-v12-4-09271f583dc6@oss.qualcomm.com/ Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
… SDHC nodes Qualcomm Inline Crypto Engine (ICE) platform driver now, supports an optional OPP-table. Add OPP-table for ICE UFS and ICE SDHC device nodes for Monaco platform. Link: https://lore.kernel.org/all/20260824-enable-ice-clock-scaling-v12-5-09271f583dc6@oss.qualcomm.com/ Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Added LT9611UXD DSI to HDMI bridge node with dual DSI ports, regulators, reset GPIO, and IRQ on I2C2 at address 0x41. Signed-off-by: Mohit Dsor <mohit.dsor@oss.qualcomm.com> Upstream-Status: Pending
In order to compute the right lag, it is required to update time to 'now'. Without this, the delayed entity might appear younger than it really is and receive less compensation for having waited. Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Add the Iris video codec device tree node for the Shikra platform. Shikra reuses the QCM2290-class video hardware and programming model. The video node is added to describe the Iris based video decoder encoder block, allowing the media driver to probe and initialize the hardware. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260722-shikra_vpu-v5-3-3d80babd4672@oss.qualcomm.com
Enable video en/decoder on the Shikra EVK board. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260722-shikra_vpu-v5-4-3d80babd4672@oss.qualcomm.com
…GMII clocks Add support for 2.5MHz and 25MHz GCC EMAC RGMII clock frequencies required for EMAC 10M and 100M speeds respectively on Qualcomm Shikra SoC. Tested-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260722-b4-shikra-gcc-emac-freqs-v2-1-2e480e2de8de@oss.qualcomm.com
SoC LPM stats are present in RPM MSGRAM and subsystem LPM stats are present in SMEM for Shikra. A generic "qcom,rpm-stats" compatible only reads SoC LPM stats like vmin and vlow. Document shikra rpm compatible to read subsystem LPM stats too along with SoC LPM stats. Reviewed-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260713-shikra_stats-v3-1-4be17121729d@oss.qualcomm.com
SoC LPM stats are present in RPM MSGRAM and subsystem LPM stats are present in SMEM for Shikra. For earlier targets using RPM processor like msm8974, rpm_master_stat.c was used for subsystem LPM stats since those stats were populated in RPM MSGRAM. Here is a brief summary of previous targets and their stats configuration, along with the drivers used to display them. +---------------|----------------------------|---------------------------+ | SoC | subsystem LPM stats | SoC LPM stats | |---------------|----------------------------|---------------------------| | msm8974, | RPM processor MSGRAM | RPM processor MSGRAM | | msm8226 | (rpm_master_stat.c) | (qcom_stats.c) | |---------------|----------------------------|---------------------------| | sm6350, | SMEM (DDR) | AOP processor MSGRAM | | sdm845, etc. | (qcom_stats.c) | (qcom_stats.c) | |---------------|----------------------------|---------------------------| | Shikra | SMEM (DDR) | RPM processor MSGRAM | | | (qcom_stats.c) | (qcom_stats.c) | +---------------|----------------------------|---------------------------+ qcom_stats.c supports both the configurations for shikra, reading subsystem LPM stats from SMEM and reading SoC LPM stats from RPM MSGRAM. A generic "qcom,rpm-stats" compatible only reads SoC LPM stats like vmin and vlow. Add shikra rpm compatible and config to read subsystem LPM stats too along with SoC LPM stats. Below is an example showing LPM stats for "apss" subsystem with this change: cat /sys/kernel/debug/qcom_stats/apss Count: 2192 Last Entered At: 5498618336 Last Exited At: 5498708046 Accumulated Duration: 2046572620. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260713-shikra_stats-v3-2-4be17121729d@oss.qualcomm.com
…C specific A generic "qcom,rpm-stats" compatible only reads stats for SoC level LPM stats like vmin and vlow. Shikra SoC specific compatible allows reading individual subsystem level LPM stats along with SoC level LPM stats. Change it. Keep "qcom,rpm-stats" as fallback compatible. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260713-shikra_stats-v3-3-4be17121729d@oss.qualcomm.com
Add support for the Qualcomm Shikra SoC to the protection domain mapper. All Shikra SoC variants (CQM, CQS, IQS) share the same protection domain requirements: mpss_wlan_pd. Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
…errupt routing The intr_target_width field sets the mask width used when writing target processor into interrupt config register and deciding which processor receives summary interrupt for a given GPIO. Without it, pinctrl driver defaults to a 3-bit mask. On Shikra, this field is 4 bits wide, which could corrupt adjacent bits and mis-route interrupts. Set intr_target_width = 4 to match the hardware. Fixes: 9db68ec ("pinctrl: qcom: Add Shikra pinctrl driver") Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260728-shikra-pinctrl-intr-width-v1-1-46583734d808@oss.qualcomm.com/
…new SoC strictness split Couple of already merged SoCs(like sc7280, sm8750, kaanapali etc.) describe ICE as single clock historically which are recently updated with mandatory 2 clocks. Keep only the known legacy compatibles flexible, and make strict validation default(of power-domains and 2 clocks) for all other Soc compatibles. This ensures old DTs are valid while ensuring any new SoC (like hawi, milos, eliza, nord, maili or any upcoming ones) must follow latest requirements by default. Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260714-b4-shikra_crypto_changse-v4-1-06a4ea97c209@oss.qualcomm.com
…kra ICE Document the Inline Crypto Engine (ICE) on the Qualcomm Shikra platform. Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260714-b4-shikra_crypto_changse-v4-2-06a4ea97c209@oss.qualcomm.com
Document shikra compatible for the True Random Number Generator. Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260714-b4-shikra_crypto_changse-v4-3-06a4ea97c209@oss.qualcomm.com
…gine Document the crypto engine on the Qualcomm Shikra platform. Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260714-b4-shikra_crypto_changse-v4-4-06a4ea97c209@oss.qualcomm.com
Qualcomm Shikra platform describes the BAM DMA node with 7 iommus entries. The current schema limit to 6, so update the binding to allow up to 7 entries. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260714-b4-shikra_crypto_changse-v4-5-06a4ea97c209@oss.qualcomm.com
# Conflicts: # drivers/bluetooth/hci_qca.c
# Conflicts: # MAINTAINERS # drivers/remoteproc/qcom_q6v5_pas.c
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile
# Conflicts: # arch/arm64/boot/dts/qcom/monaco-evk.dts # arch/arm64/boot/dts/qcom/monaco.dtsi
# Conflicts: # arch/arm64/boot/dts/qcom/agatti.dtsi
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile # arch/arm64/boot/dts/qcom/talos.dtsi
# Conflicts: # arch/arm64/boot/dts/qcom/qcs8300-ride.dts # drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
# Conflicts: # drivers/firmware/qcom/Kconfig # drivers/firmware/qcom/Makefile
# Conflicts: # Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml # arch/arm64/configs/defconfig # drivers/dma/qcom/bam_dma.c
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
… EVK" Compilation breaking with this change, so revert for now. This reverts commit 8c9d598. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
Compilation breaking with this change, so revert for now. This reverts commit 9455e01. Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
Test Matrix
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Shikra CQM and CQS are retail variants sharing the same PM4125 PMIC and identical camera supply rails. The only difference between them is the integrated modem on CQM, which does not affect camera hardware. Add a shared overlay for optional IMX577 integration via CSIPHY1, used by both CQM and CQS EVK boards. Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
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Name SHA Commits
tech/bsp/clk 24b9b5e 32
tech/bsp/devfreq 4809534 7
tech/security/firmware-smc de7413c 6
tech/bsp/soc-infra ff6ff7b 22
tech/bsp/pinctrl 79149ef 1
tech/bsp/remoteproc 39a86aa 13
tech/bus/peripherals 158e733 17
tech/bus/pci/all 99d5cf2 45
tech/bus/pci/phy 66e44c2 14
tech/bus/usb/dwc d90fb64 4
tech/bus/usb/phy c3aa7d5 35
tech/debug/hwtracing a3f730f 24
tech/pmic/misc e279b1a 23
tech/mem/iommu cdc9e80 9
tech/mm/audio/all 88b8f29 8
tech/mm/camss 94954b3 44
tech/mm/drm a18271a 81
tech/mm/fastrpc 1bc7df1 11
tech/mm/video 00e60cd 128
tech/mm/gpu 2452d5e 14
tech/mproc/rpmsg 55dc464 1
tech/net/ath 7ce170e 53
tech/net/bluetooth 450dc5e 7
tech/pm/power f712532 16
tech/pm/thermal d525ff9 8
tech/security/crypto 1f60c0a 23
tech/security/ice dc34f45 14
tech/storage/all cb6192d 7
tech/all/dt/qcs6490 2e92fd1 28
tech/all/dt/qcs9100 20a19cd 26
tech/all/dt/qcs8300 fbca2cb 35
tech/all/dt/qcs615 66b7e2f 11
tech/all/dt/agatti 2ca1b63 2
tech/all/dt/eliza 5338032 25
tech/all/dt/hamoa affc288 49
tech/all/dt/glymur c5bf216 60
tech/all/dt/kaanapali d21ef73 26
tech/all/dt/pakala 0aca0eb 14
tech/all/config e2a07da 80
tech/overlay/dt f65c8a0 81
tech/all/workaround 42fd140 13
tech/mproc/all 104969c 2
tech/noup/debug/all 1a2ad89 32
tech/hwe/unoq a2d85fe 4
tech/all/shikra 4c5d455 188
early/hwe/lyra 9b425c8 14