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Fix a bug of $ROOT path when using path dependency #348

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12 changes: 6 additions & 6 deletions src/script_fmt/formality_tcl.tera
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ set search_path_initial $search_path
{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if group.file_type == 'verilog' or group.file_type == 'vhdl' %}{% if source_annotations %}
# {{ group.metadata }}{% endif %}
set search_path $search_path_initial
{% for incdir in group.incdirs %}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
{% for incdir in group.incdirs %}lappend search_path "${ROOT}{{ incdir | replace(from=root, to='') }}"
{% endfor %}
{% if abort_on_error %}if {[catch { {% endif %}{% if group.file_type == 'verilog' %}read_sverilog{% elif group.file_type == 'vhdl' %}read_vhdl{% endif %} -r \
{% for define in group.defines %}{% if loop.first %}-define { \
Expand All @@ -14,19 +14,19 @@ set search_path $search_path_initial
{% else %} \
{% endif %}{% endfor %}[list \
{% for file in group.files %}{% if source_annotations %}{% if file.comment %}{{ ' ' }}# {{ file.comment }}
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='${ROOT}') }}" \
{% endfor %}]
{% if abort_on_error %}}]} {return 1}{% endif %}
{% else %}{% if source_annotations %}
# {{ group.metadata }}{% endif %}
# Skipping {{ group.files | length }} file(s) of unknown type (prefix with sv:/v:/vhd: to set one):
{% for file in group.files %}# {{ file.file | replace(from=root, to='$ROOT') }}
{% for file in group.files %}# {{ file.file | replace(from=root, to='${ROOT}') }}
{% endfor %}{% endif %}{% endfor %}
{# Common compilation: all files in one block -#}
{% else -%}
{# Verilog sources -#}
{%- for file in all_verilog %}{% if loop.first %}set search_path $search_path_initial
{% for incdir in all_incdirs %}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
{% for incdir in all_incdirs %}lappend search_path "${ROOT}{{ incdir | replace(from=root, to='') }}"
{% endfor %}
{% if abort_on_error %}if {[catch { {% endif %}read_sverilog -r \
{% for define in all_defines %}{% if loop.first %}-define { \
Expand All @@ -35,15 +35,15 @@ set search_path $search_path_initial
{% else %} \
{% endif %}{% endfor %}[list \
{% endif %}{% if source_annotations %}{% if file.comment %}{{ ' ' }}# {{ file.comment }}
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='${ROOT}') }}" \
{% if loop.last %}]
{% if abort_on_error %}}]} {return 1}{% endif %}
{% endif %}{% endfor %}
{# VHDL sources -#}
{% for file in all_vhdl %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}read_vhdl -r \
[list \
{% endif %}{% if source_annotations %}{% if file.comment %}{{ ' ' }}# {{ file.comment }}
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='${ROOT}') }}" \
{% if loop.last %}]
{% if abort_on_error %}}]} {return 1}{% endif %}
{% endif %}{% endfor %}
Expand Down
12 changes: 6 additions & 6 deletions src/script_fmt/genus_tcl.tera
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ set ROOT "{{ root }}"
{% if compilation_mode == 'separate' %}{% for group in srcs %}{% if group.file_type == 'verilog' or group.file_type == 'vhdl' %}{% if source_annotations %}
# {{ group.metadata }}{% endif %}
set search_path $search_path_initial
{% for incdir in group.incdirs %}lappend search_path "{{ incdir | replace(from=root, to='$ROOT') }}"
{% for incdir in group.incdirs %}lappend search_path "{{ incdir | replace(from=root, to='${ROOT}') }}"
{% endfor %}set_db init_hdl_search_path $search_path

{% if group.file_type == 'verilog' %}read_hdl -language sv \
Expand All @@ -20,18 +20,18 @@ set search_path $search_path_initial
{% else %} \
{% endif %}{% endfor %}[list \
{% for file in group.files %}{% if source_annotations %}{% if file.comment %}{{ ' ' }}# {{ file.comment }}
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='${ROOT}') }}" \
{% endfor %}]
{% else %}{% if source_annotations %}
# {{ group.metadata }}{% endif %}
# Skipping {{ group.files | length }} file(s) of unknown type (prefix with sv:/v:/vhd: to set one):
{% for file in group.files %}# {{ file.file | replace(from=root, to='$ROOT') }}
{% for file in group.files %}# {{ file.file | replace(from=root, to='${ROOT}') }}
{% endfor %}{% endif %}{% endfor %}
{# Common compilation: all files in one block -#}
{% else -%}
{# Verilog sources -#}
{%- for file in all_verilog %}{% if loop.first %}set search_path $search_path_initial
{% for incdir in all_incdirs %}lappend search_path "$ROOT{{ incdir | replace(from=root, to='') }}"
{% for incdir in all_incdirs %}lappend search_path "${ROOT}{{ incdir | replace(from=root, to='') }}"
{% endfor %}
set_db init_hdl_search_path $search_path

Expand All @@ -42,7 +42,7 @@ set_db init_hdl_search_path $search_path
{% else %} \
{% endif %}{% endfor %}[list \
{% endif %}{% if source_annotations %}{% if file.comment %}{{ ' ' }}# {{ file.comment }}
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='${ROOT}') }}" \
{% if loop.last %}]
{% if abort_on_error %}}]} {return 1}{% endif %}
{% endif %}{% endfor %}
Expand All @@ -51,7 +51,7 @@ set_db init_hdl_search_path $search_path
{% if abort_on_error %}if {[catch { {% endif %}read_hdl -language vhdl \
[list \
{% endif %}{% if source_annotations %}{% if file.comment %}{{ ' ' }}# {{ file.comment }}
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='${ROOT}') }}" \
{% if loop.last %}]
{% if abort_on_error %}}]} {return 1}{% endif %}
{% endif %}{% endfor %}
Expand Down
12 changes: 6 additions & 6 deletions src/script_fmt/riviera_tcl.tera
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Original file line number Diff line number Diff line change
Expand Up @@ -6,17 +6,17 @@ vlib work
{% endif %}{% if abort_on_error %}if {[catch { {% endif %}{% if group.file_type == 'verilog' %}vlog -sv \
{% for tmp_arg in vlog_args %}{{ tmp_arg }} \
{% endfor %}{% for define in group.defines %}"+define+{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}" \
{% endfor %}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
{% endfor %}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='${ROOT}') }}" \
{% endfor %}{% elif group.file_type == 'vhdl' %}vcom -2008 \
{% for tmp_arg in vcom_args %}{{ tmp_arg }} \
{% endfor %}{% endif %}{% for file in group.files %}{% if source_annotations %}{% if file.comment %}# {{ file.comment }}
{% endif %}{% endif %}"{{ file.file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
{% endif %}{% endif %}"{{ file.file | replace(from=root, to='${ROOT}') }}" {% if not loop.last %}\
{% else %}\
{% endif %}{% endfor %}{% if abort_on_error %}}]} {return 1}{% endif %}

{% else %}{% if source_annotations %}# {{ group.metadata }}
{% endif %}# Skipping {{ group.files | length }} file(s) of unknown type (prefix with sv:/v:/vhd: to set one):
{% for file in group.files %}# {{ file.file | replace(from=root, to='$ROOT') }}
{% for file in group.files %}# {{ file.file | replace(from=root, to='${ROOT}') }}
{% endfor %}
{% endif %}{% endfor -%}
{# Common compilation: all files in one block -#}
Expand All @@ -25,9 +25,9 @@ vlib work
{%- for file in all_verilog %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}vlog -sv \
{% for tmp_arg in vlog_args %}{{ tmp_arg }} \
{% endfor %}{% for define in all_defines %}"+define+{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}" \
{% endfor %}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
{% endfor %}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='${ROOT}') }}" \
{% endfor %}{% endif %}{% if source_annotations %}{% if file.comment %}# {{ file.comment }}
{% endif %}{% endif %}"{{ file.file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
{% endif %}{% endif %}"{{ file.file | replace(from=root, to='${ROOT}') }}" {% if not loop.last %}\
{% else %}\
{% endif %}{% if loop.last %}{% if abort_on_error %}}]} {return 1}{% endif %}

Expand All @@ -36,7 +36,7 @@ vlib work
{%- for file in all_vhdl %}{% if loop.first %}{% if abort_on_error %}if {[catch { {% endif %}vcom -2008 \
{% for tmp_arg in vcom_args %}{{ tmp_arg }} \
{% endfor %}{% endif %}{% if source_annotations %}{% if file.comment %}# {{ file.comment }}
{% endif %}{% endif %}"{{ file.file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
{% endif %}{% endif %}"{{ file.file | replace(from=root, to='${ROOT}') }}" {% if not loop.last %}\
{% else %}\
{% endif %}{% if loop.last %}{% if abort_on_error %}}]} {return 1}{% endif %}

Expand Down
12 changes: 6 additions & 6 deletions src/script_fmt/synopsys_tcl.tera
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ set search_path_initial $search_path
# {{ group.metadata }}{% endif %}
set search_path $search_path_initial
{% for incdir in group.incdirs -%}
lappend search_path "{{ incdir | replace(from=root, to='$ROOT') }}"
lappend search_path "{{ incdir | replace(from=root, to='${ROOT}') }}"
{% endfor %}
{% if abort_on_error %}if {0 == [{% endif -%}
analyze -format {% if group.file_type == 'verilog' %}sv{% elif group.file_type == 'vhdl' %}vhdl{% endif %} \
Expand All @@ -26,21 +26,21 @@ analyze -format {% if group.file_type == 'verilog' %}sv{% elif group.file_type =
{% endif %}{% endfor %}[list \
{% for file in group.files -%}
{%- if source_annotations %}{% if file.comment %}{{ ' ' }}# {{ file.comment }}
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='${ROOT}') }}" \
{% endfor %}]
{% if abort_on_error %}]} {return 1}{% endif %}
{% else %}{% if source_annotations %}
# {{ group.metadata }}{% endif %}
# Skipping {{ group.files | length }} file(s) of unknown type (prefix with sv:/v:/vhd: to set one):
{% for file in group.files %}# {{ file.file | replace(from=root, to='$ROOT') }}
{% for file in group.files %}# {{ file.file | replace(from=root, to='${ROOT}') }}
{% endfor %}{% endif %}{% endfor %}
{# Common compilation: all files in one block -#}
{% else -%}
{# Verilog sources -#}
{%- for file in all_verilog -%}
{%- if loop.first %}set search_path $search_path_initial
{% for incdir in all_incdirs -%}
lappend search_path "{{ incdir | replace(from=root, to='$ROOT') }}"
lappend search_path "{{ incdir | replace(from=root, to='${ROOT}') }}"
{% endfor %}
{% if abort_on_error %}if {0 == [{% endif -%}
analyze -format sv \
Expand All @@ -53,7 +53,7 @@ analyze -format sv \
{% else %} \
{% endif %}{% endfor %}[list \
{% endif %}{% if source_annotations %}{% if file.comment %}{{ ' ' }}# {{ file.comment }}
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='${ROOT}') }}" \
{% if loop.last %}]
{% if abort_on_error %}]} {return 1}{% endif %}
{% endif %}{% endfor %}
Expand All @@ -65,7 +65,7 @@ analyze -format vhdl \
{% endfor -%}
[list \
{% endif %}{% if source_annotations %}{% if file.comment %}{{ ' ' }}# {{ file.comment }}
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='$ROOT') }}" \
{% endif %}{% endif %}{{ ' ' }}"{{ file.file | replace(from=root, to='${ROOT}') }}" \
{% if loop.last %}]
{% if abort_on_error %}]} {return 1}{% endif %}
{% endif %}{% endfor %}
Expand Down
12 changes: 6 additions & 6 deletions src/script_fmt/vcs_sh.tera
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Expand Up @@ -11,15 +11,15 @@ ROOT="{{ root }}"
-full64 \
{% for tmp_arg in vlogan_args %}{{ tmp_arg }} \
{% endfor %}{% for define in group.defines %}"+define+{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}" \
{% endfor %}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
{% endfor %}{% for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='${ROOT}') }}" \
{% endfor %}{% elif group.file_type == 'vhdl' %}{{ vhdlan_bin }} \
{% for tmp_arg in vhdlan_args %}{{ tmp_arg }} \
{% endfor %}{% endif %}{% for file in group.files %}"{{ file.file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
{% endfor %}{% endif %}{% for file in group.files %}"{{ file.file | replace(from=root, to='${ROOT}') }}" {% if not loop.last %}\
{% endif %}{% endfor %}
{% else %}{% if source_annotations %}
# {{ group.metadata }}{% endif %}
# Skipping {{ group.files | length }} file(s) of unknown type (prefix with sv:/v:/vhd: to set one):
{% for file in group.files %}# {{ file.file | replace(from=root, to='$ROOT') }}
{% for file in group.files %}# {{ file.file | replace(from=root, to='${ROOT}') }}
{% endfor %}{% endif %}{% endfor %}
{# Common compilation: all files in one block -#}
{% else -%}
Expand All @@ -28,14 +28,14 @@ ROOT="{{ root }}"
-full64 \
{% for tmp_arg in vlogan_args %}{{ tmp_arg }} \
{% endfor %}{% for define in all_defines %}"+define+{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}" \
{% endfor %}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
{% endfor %}{% endif %}"{{ file.file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
{% endfor %}{% for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='${ROOT}') }}" \
{% endfor %}{% endif %}"{{ file.file | replace(from=root, to='${ROOT}') }}" {% if not loop.last %}\
{% endif %}{% if loop.last %}
{% endif %}{% endfor %}
{# VHDL sources -#}
{% for file in all_vhdl %}{% if loop.first %}{{ vhdlan_bin }} \
{% for tmp_arg in vhdlan_args %}{{ tmp_arg }} \
{% endfor %}{% endif %}"{{ file.file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
{% endfor %}{% endif %}"{{ file.file | replace(from=root, to='${ROOT}') }}" {% if not loop.last %}\
{% endif %}{% if loop.last %}
{% endif %}{% endfor %}
{% endif %}
6 changes: 3 additions & 3 deletions src/script_fmt/vivado_tcl.tera
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Original file line number Diff line number Diff line change
Expand Up @@ -6,23 +6,23 @@ set ROOT "{{ root }}"
{% if source_annotations %}# {{ group.metadata }}
{% endif %}add_files -norecurse -fileset [current_fileset] [list \
{% for file in group.files %}{% if source_annotations %}{% if file.comment %}# {{ file.comment }}
{% endif %}{% endif %}{{ file.file | replace(from=root, to='$ROOT') }} \
{% endif %}{% endif %}{{ file.file | replace(from=root, to='${ROOT}') }} \
{% if not loop.last %} {% endif %}{% endfor %}]
{% endfor -%}
{# Common compilation: all files in one block -#}
{%- else -%}
{%- for file in all_files -%}
{%- if loop.first %}add_files -norecurse -fileset [current_fileset] [list \
{% endif %}{% if source_annotations %}{% if file.comment %}# {{ file.comment }}
{% endif %}{% endif %}{{ file.file | replace(from=root, to='$ROOT') }} \
{% endif %}{% endif %}{{ file.file | replace(from=root, to='${ROOT}') }} \
{% if not loop.last %} {% endif %}{% if loop.last %}]
{% endif %}{% endfor %}{% endif -%}
{# Set include directories and defines for each fileset -#}
{%- for arg in vivado_filesets -%}
{%- for incdir in all_incdirs -%}
{%- if loop.first %}
set_property include_dirs [list \
{% endif %}{{incdir | replace(from=root, to='$ROOT') }}{%if loop.last %} \
{% endif %}{{incdir | replace(from=root, to='${ROOT}') }}{%if loop.last %} \
] [current_fileset{{ arg }}]
{% else %} \
{% endif %}{% endfor %}{% endfor -%}
Expand Down
12 changes: 6 additions & 6 deletions src/script_fmt/vsim_tcl.tera
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Original file line number Diff line number Diff line change
Expand Up @@ -11,15 +11,15 @@ set ROOT "{{ root }}"
{% endfor -%}
{%- for define in group.defines %}"+define+{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}" \
{% endfor -%}
{%- for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
{%- for incdir in group.incdirs %}"+incdir+{{ incdir | replace(from=root, to='${ROOT}') }}" \
{% endfor -%}
{%- elif group.file_type == 'vhdl' %}vcom -2008 \
{% for tmp_arg in vcom_args %}{{ tmp_arg }} \
{% endfor -%}
{%- endif -%}
{%- for file in group.files -%}
{%- if source_annotations %}{% if file.comment %}# {{ file.comment }}
{% endif %}{% endif %}"{{ file.file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
{% endif %}{% endif %}"{{ file.file | replace(from=root, to='${ROOT}') }}" {% if not loop.last %}\
{% endif -%}
{%- endfor -%}
{%- if abort_on_error %}\
Expand All @@ -28,7 +28,7 @@ set ROOT "{{ root }}"
{% if source_annotations %}# {{ group.metadata }}
{% endif -%}
# Skipping {{ group.files | length }} file(s) of unknown type (prefix with sv:/v:/vhd: to set one):
{% for file in group.files %}# {{ file.file | replace(from=root, to='$ROOT') }}
{% for file in group.files %}# {{ file.file | replace(from=root, to='${ROOT}') }}
{% endfor -%}
{% endif %}{% endfor -%}
{# Common compilation: all files in one block -#}
Expand All @@ -41,10 +41,10 @@ vlog -incr -sv \
{% endfor -%}
{%- for define in all_defines %}"+define+{{ define.0 }}{% if define.1 %}={{ define.1 }}{% endif %}" \
{% endfor -%}
{%- for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='$ROOT') }}" \
{%- for incdir in all_incdirs %}"+incdir+{{ incdir | replace(from=root, to='${ROOT}') }}" \
{% endfor -%}
{%- endif %}{% if source_annotations %}{% if file.comment %}# {{ file.comment }}
{% endif %}{% endif %}"{{ file.file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
{% endif %}{% endif %}"{{ file.file | replace(from=root, to='${ROOT}') }}" {% if not loop.last %}\
{% endif -%}
{%- if loop.last %}{% if abort_on_error %} \
}]} {return 1}{% endif %}
Expand All @@ -56,7 +56,7 @@ vcom -2008 \
{% for tmp_arg in vcom_args %}{{ tmp_arg }} \
{% endfor -%}
{%- endif %}{% if source_annotations %}{% if file.comment %}# {{ file.comment }}
{% endif %}{% endif %}"{{ file.file | replace(from=root, to='$ROOT') }}" {% if not loop.last %}\
{% endif %}{% endif %}"{{ file.file | replace(from=root, to='${ROOT}') }}" {% if not loop.last %}\
{% endif -%}
{%- if loop.last %}{% if abort_on_error %} \
}]} {return 1}{% endif %}
Expand Down
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