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[ARM] Restore cache information - #292

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chaitu236 wants to merge 2 commits into
ni:nilrt/master/6.18from
chaitu236:dev/cvadrevu/arm_cache
Open

[ARM] Restore cache information#292
chaitu236 wants to merge 2 commits into
ni:nilrt/master/6.18from
chaitu236:dev/cvadrevu/arm_cache

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@chaitu236

@chaitu236 chaitu236 commented Aug 29, 2026

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Restore cache information for ARM targets on 6.18 kernel that was previously implemented in 4.14 with 111fd34 and 8bb1a5f which these commits replace.

ARM version of libniCPULib expects raw bytes instead of 32K, etc so add a compatibility commit.

WI: AB#3990506

Testing

  • Built kernel and booted on cRIO-9068
  • Ran following to validate that LV APIs work
import ctypes

path = "/usr/local/natinst/labview/libniCPULib.so.26.3.0"
lib = ctypes.CDLL(path)

lib.DataCacheSize.argtypes = [ctypes.c_uint]
lib.DataCacheSize.restype = ctypes.c_uint64

lib.DataCacheEntrySize.argtypes = [ctypes.c_uint]
lib.DataCacheEntrySize.restype = ctypes.c_uint

lib.DataCacheEntryType.argtypes = [ctypes.c_uint]
lib.DataCacheEntryType.restype = ctypes.c_uint

for level in range(5):
    print(
        level,
        "size=", lib.DataCacheSize(level),
        "entry_size=", lib.DataCacheEntrySize(level),
        "type=", lib.DataCacheEntryType(level),
    )

Describe the Cortex-A9 L1 cache geometry and link both CPUs to the
shared PL310 L2 cache. Add the L2 cache geometry as well.

This allows the generic cacheinfo framework to expose cache size, line
size, set count, associativity, and sharing information through sysfs.

Assisted-by: Copilot:GPT-5.6-Sol
Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
Released NI ARM software expects cache size attributes in sysfs to be
reported as bytes, matching the format provided by older NI kernels.
The generic cacheinfo implementation reports sizes with a K suffix,
which causes existing LabVIEW CPU information code to interpret a 32K
cache as 32 bytes.

Add an NI ARM compatibility option that reports cache sizes in bytes
and enable it for NI Zynq targets. Other platforms retain the standard
generic cacheinfo format.

Assisted-by: Copilot:GPT-5.6-Sol
Signed-off-by: Chaitanya Vadrevu <chaitanya.vadrevu@emerson.com>
@chaitu236
chaitu236 requested a review from a team August 29, 2026 00:59
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