feat(dfx): profile A5 HBG AICore scheduler - #2104
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📝 WalkthroughWalkthroughThe change adds AICore and AICPU scheduler profiling support. It introduces stream-based scheduler records, lifecycle records, chip-swimlane JSON extensions, producer-aware trace rendering, legacy input fallback, and scheduler terminology updates. ChangesScheduler profiling pipeline
Estimated code review effort: 5 (Critical) | ~120 minutes Merge Risk: 🟡 Moderate · up to Profiling-enabled runs can produce corrupted or misleading artifacts, validate stale output, or fail during extension publication and cleanup. These issues should be fixed before merge. Sequence Diagram(s)sequenceDiagram
participant AICoreScheduler
participant RuntimeMaker
participant HostApi
participant ChipSwimlaneCollector
participant SwimlaneConverter
AICoreScheduler->>RuntimeMaker: record scheduler and lifecycle activity
RuntimeMaker->>HostApi: publish profiling JSON extensions
HostApi->>ChipSwimlaneCollector: store scheduler_records and lifecycle records
ChipSwimlaneCollector->>SwimlaneConverter: provide chip_swimlane_records.json
SwimlaneConverter->>SwimlaneConverter: parse streams and generate Chrome trace events
Poem
🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
Full details: Docstring CoverageExplanation Docstring coverage is 13.37% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 172 functions across 34 files. (5 skipped: 5 unsupported.)
✨ Finishing Touches 💡 1🛠️ Fix failing CI checks 💡
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Inline comments:
In `@simpler_setup/tools/swimlane_converter.py`:
- Around line 1571-1572: Update the interval filter in read_perf_data() so a
start value of 0.0 is retained; skip only intervals whose end is not positive or
whose end precedes start, while preserving valid lifecycle intervals.
- Around line 591-593: Update the AICore-only handling in the swimlane
conversion and print_task_statistics flow to detect valid AICPU timestamps from
task rows rather than chip_swimlane_level. Do not assign or report synthetic
AICPU timings when no valid AICPU timestamps exist, and use the same task-row
timestamp condition for the AICore observed-span fallback.
- Around line 347-349: Update the metric merge in the record-processing flow to
reject any metric whose keys intersect with the fixed record_fields set, rather
than allowing those values to overwrite validated scheduler-record fields.
Preserve the existing exclusion of record_index and ensure invalid metrics are
rejected before merged_records is updated.
In `@src/a5/runtime/host_build_graph/runtime/scheduler/scheduler_ready.h`:
- Around line 1061-1076: Move the SchedulerTaskTrace writes and both
scheduler_publish_cache_line calls in the trace_enabled block so they complete
before scheduler_gm_publish(slot->publication, ...), ensuring the dispatch trace
is published before the READY slot becomes visible. Preserve the existing trace
fields and commit_task_trace flow.
In `@src/common/platform/include/common/host_api.h`:
- Around line 260-263: Update HostApi::publish_chip_swimlane_extension in
src/common/platform/include/common/host_api.h (lines 260-263) to catch
exceptions from the callback invocation and return false while preserving the
existing null checks and success behavior. The affected wrapper call sites in
src/common/platform/onboard/host/c_api_shared.cpp (lines 209-212) and
src/common/platform/sim/host/c_api_shared.cpp (lines 193-196) require no direct
changes; they are covered by the HostApi boundary fix.
In `@src/common/platform/shared/host/chip_swimlane_collector.cpp`:
- Around line 86-103: Update ChipSwimlaneCollector::set_json_extension to parse
json_value as JSON after validating its basic boundaries, and return false when
parsing fails; only add successfully parsed values to json_extensions_. Preserve
the existing section-name and duplicate checks, and keep storing the original
JSON text for valid input.
In `@src/common/platform/sim/host/device_runner_base.h`:
- Around line 287-288: Clear deferred producer state during abandon and
finalization in both DeviceRunnerBase implementations. Add a clear-only reset
for chip_swimlane_extension_producer_ctx_ and chip_swimlane_extension_producer_,
then invoke it from every abandon and finalization path so
publish_aicore_scheduler_profiling_extension() cannot retain a destroyed Runtime
context. Update both src/common/platform/sim/host/device_runner_base.h lines
287-288 and src/common/platform/onboard/host/device_runner_base.h lines 747-748;
both sites require the same reset integration.
- Around line 284-290: Update publish_chip_swimlane_extensions to catch
exceptions thrown by the producer invocation, return false on failure, and
preserve the existing null-producer success behavior so callers use their
warning path and continue export.
In `@tests/st/a5/host_build_graph/single_core_dag/test_single_core_dag.py`:
- Line 102: The profiling assertion currently discovers output directories by
timestamp, which can select stale results when directory mtimes tie. Update
build_output_prefix() to create a unique directory for each invocation, then
pass that exact prefix through to the validator instead of filtering
_outputs_dir() with run_marker.
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📒 Files selected for processing (39)
simpler_setup/tools/README.mdsimpler_setup/tools/sched_overhead_analysis.pysimpler_setup/tools/swimlane_converter.pysrc/a2a3/platform/include/common/scheduler_profiling.hsrc/a2a3/platform/onboard/host/device_runner.cppsrc/a2a3/platform/sim/host/device_runner.cppsrc/a2a3/runtime/host_build_graph/docs/profiling_levels.mdsrc/a2a3/runtime/tensormap_and_ringbuffer/docs/profiling_levels.mdsrc/a2a3/runtime/tensormap_and_ringbuffer/runtime/runtime.hsrc/a5/platform/include/common/scheduler_profiling.hsrc/a5/platform/onboard/host/device_runner.cppsrc/a5/platform/sim/host/device_runner.cppsrc/a5/runtime/host_build_graph/aicore/aicore_executor.cppsrc/a5/runtime/host_build_graph/aicpu/aicore_lifecycle.cppsrc/a5/runtime/host_build_graph/docs/profiling_levels.mdsrc/a5/runtime/host_build_graph/host/runtime_maker.cppsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_completion.hsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_dispatch.hsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_layout.hsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_ready.hsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_topology.hsrc/a5/runtime/host_build_graph/runtime/scheduler/scheduler_types.hsrc/a5/runtime/tensormap_and_ringbuffer/docs/profiling_levels.mdsrc/a5/runtime/tensormap_and_ringbuffer/runtime/runtime.hsrc/common/host_build_graph/runtime.hsrc/common/platform/include/common/chip_swimlane_profiling.hsrc/common/platform/include/common/host_api.hsrc/common/platform/include/host/chip_swimlane_collector.hsrc/common/platform/onboard/host/c_api_shared.cppsrc/common/platform/onboard/host/device_runner_base.cppsrc/common/platform/onboard/host/device_runner_base.hsrc/common/platform/shared/host/chip_swimlane_collector.cppsrc/common/platform/sim/host/c_api_shared.cppsrc/common/platform/sim/host/device_runner_base.htests/st/a5/host_build_graph/single_core_dag/test_single_core_dag.pytests/ut/cpp/a5/test_hbg_scheduler_dispatch.cpptests/ut/cpp/a5/test_hbg_scheduler_ready.cpptests/ut/py/test_sched_overhead_analysis.pytests/ut/py/test_swimlane_converter.py
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Use Scheduler consistently for the resident AICore worker role. Rename its state, helpers, constants, and tests without changing behavior.
Move A2/A3 and A5 scheduler record ABIs into their architecture trees. Share host-only JSON serialization while preserving schema version 1. Restrict runtime extensions to fixed artifact slots and select their publishers when each host runtime is linked. Keep the converter compatible with legacy scheduler artifacts.
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Record AICore task timing, AICPU lifecycle, and real Scheduler intervals. Stage pre-kernel timestamps outside the callable live set and let the Scheduler consolidate each task trace before publishing valid. Keep bootstrap fanin writes on their owned cache line so they cannot overwrite completed task identity on hardware. Provide the A5 HBG runtime publisher for resident scheduler state. Coalesce consecutive idle iterations so fixed-capacity phase capture remains bounded when host simulation is CPU constrained.
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Summary
scheduler_recordsschema while keeping architecture-owned device ABIs and a shared host-only JSON serializer.Commit structure
Refactor: rename A5 HBG Resolver to Scheduler— terminology-only rename.Support: unify chip-swimlane scheduler schema— cross-platform schema migration, shared host-only serializer, and narrowed extension API.Support: profile A5 HBG AICore scheduler— A5 HBG profiling implementation and its cache-publication/idle-capture correctness fixes.Validation
producer=aicpu; Level 3/4 contain 19 scheduler phases with zero dropped records; Level 4 contains all 5 AICPU orchestrator records.