Enable trace in OperatorSequence - #178
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Trace lowering records the buffer's index in the sequence it configures, but that index is resolved against the kernel the host dispatches, which for a fused build is the wrapper rather than the operator. The address was patched from an argument the wrapper did not have, so the trace DMA wrote nowhere and the buffer came back empty. Give the wrapper the buffer at the same index.
Tracing adds a runtime-sequence argument, so a traced ELF cannot be reused by an untraced run or the other way round: the two now get different artifact names and toggling the flag no longer needs the build directory wiped.
mlir-aie appends a single trace buffer to the dispatched runtime sequence and hands each configured design a slice of it. The fused sequence no longer has to place one buffer per operator at the index that operator patches against. Drop trace_argument_layout. The three consolidated buffers keep indices 0-2 and the trace buffer lands after them, so operators taking the same number of arguments no longer contend for one slot. Size the host buffer from aie.trace_slices in the lowered module. trace_size is per design and says nothing about how many channels or sub-designs claim a share. Bind the buffer at index 3 and sync it back with the outputs. Ask aiecc for --get-input-with-addresses on a traced build and read the lowered module from that path, rather than picking the work-dir file with the most write32 ops. Split the buffer by recorded slice when dumping traces, and parse each slice against the device that wrote it: sub-designs routinely occupy the same tiles, and a merged parse cannot tell their events apart.
Rewrite in the plain style: active voice, one idea per sentence, and no attribution of understanding to the parser. Match the module docstring of tracing_utils to a single trace buffer. It described one buffer per operator, which the compiler no longer produces.
Both files already load the aie bindings at import time, so a deferred import saves nothing.
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Requires upstream MLIR-AIE PR Xilinx/mlir-aie#3652
Supersedes #154