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Release 1.0.0 - #7

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accemic merged 1 commit into
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albert/release-1.0.0
Aug 28, 2026
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Release 1.0.0#7
accemic merged 1 commit into
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albert/release-1.0.0

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@accemic

@accemic accemic commented Aug 28, 2026

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The RTL is the one every verdict below was measured against; what changed since the initial public tree is that the repository became publishable and complete:

  • Two back ends, one event stream: N-Trace (Nexus messages on ATB) and E-Trace 2.0 (te_inst packets), selected per instance by synthesis parameter, with the enhanced features (DAQ / ACT-CAP, filtering, sync variants, funnel, watchpoint records, DDR rings).
  • Ingress adapters for AMD MicroBlaze V, CVA6 ITI and Rocket TCI, and the MINRES TGC5B example SoC library.
  • Nine KV260 demonstrators plus the RV/CFI demo, each with its ready-to-load prebuilt app in-tree (bitstream, overlay, manifest), the board drivers and the build tutorial; a hardware-free dashboard replaying committed captures.
  • Verification: the Verilator/xsim gate battery, the SymbiYosys property gates, the versioned evidence, the byte-neutrality references and the decoder corpus; every decode verdict is taken by CTTD, the reference decoder, pinned by tag and sha256 to the public release accemic/CTTD v2.3.0-cttd3.
  • The Reference Manual (doc/rm-ctte.pdf, doc/rm-ctte.html) next to the AsciiDoc documentation set.
  • Publication guards in make lint: language, lab internals, public links and slugs, tutorial paths, version agreement, REUSE (1318/1318 files), vendor deltas, register-map consistency.
  • Licensing per artifact type (LICENSE.md, REUSE.toml): hardware IP dual CERN-OHL-S-2.0 OR Accemic commercial, tooling ISC, documentation CC-BY-4.0, third-party cores under their own terms.

The README's "will soon be highly enhanced" banner announced this release; it goes with it. Details and the by-design limitations are in doc/release-notes.adoc.

The RTL is the one every verdict below was measured against; what
changed since the initial public tree is that the repository became
publishable and complete:

- Two back ends, one event stream: N-Trace (Nexus messages on ATB)
  and E-Trace 2.0 (te_inst packets), selected per instance by
  synthesis parameter, with the enhanced features (DAQ / ACT-CAP,
  filtering, sync variants, funnel, watchpoint records, DDR rings).
- Ingress adapters for AMD MicroBlaze V, CVA6 ITI and Rocket TCI,
  and the MINRES TGC5B example SoC library.
- Nine KV260 demonstrators plus the RV/CFI demo, each with its
  ready-to-load prebuilt app in-tree (bitstream, overlay, manifest),
  the board drivers and the build tutorial; a hardware-free dashboard
  replaying committed captures.
- Verification: the Verilator/xsim gate battery, the SymbiYosys
  property gates, the versioned evidence, the byte-neutrality
  references and the decoder corpus; every decode verdict is taken
  by CTTD, the reference decoder, pinned by tag and sha256 to the
  public release accemic/CTTD v2.3.0-cttd3.
- The Reference Manual (doc/rm-ctte.pdf, doc/rm-ctte.html) next to
  the AsciiDoc documentation set.
- Publication guards in `make lint`: language, lab internals,
  public links and slugs, tutorial paths, version agreement, REUSE
  (1318/1318 files), vendor deltas, register-map consistency.
- Licensing per artifact type (LICENSE.md, REUSE.toml): hardware IP
  dual CERN-OHL-S-2.0 OR Accemic commercial, tooling ISC,
  documentation CC-BY-4.0, third-party cores under their own terms.

The README's "will soon be highly enhanced" banner announced this
release; it goes with it. Details and the by-design limitations are in
doc/release-notes.adoc.
@accemic
accemic force-pushed the albert/release-1.0.0 branch from 802fbbe to 1e4d103 Compare August 28, 2026 11:23
@accemic
accemic merged commit 713de31 into main Aug 28, 2026
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