[OMNIML-5899] Add IQ post-training quantization recipes - #2449
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Included review availability: Your plan provides up to 12 included reviews per hour; 11 remain after this review. 📝 WalkthroughWalkthroughThe PR adds IQ1_S and IQ2_XS GGML-compatible quantizer configurations, PTQ presets, general recipes, packing-contract tests, and documentation. ChangesIQ1_S and IQ2_XS recipe support
Priority: ⬇️ Low Estimated code review effort: 2 (Simple) | ~10 minutes Change: Feature Merge Risk: ⚪ Minimal · up to The IQ recipes are accurately documented under a generic weight-only heading, and no actionable merge-blocking risk remains. 🚥 Pre-merge checks | ✅ 5 | ❌ 1❌ Failed checks (1 warning)
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| block_sizes: | ||
| -1: 256 |
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[SUGGESTION] block_sizes here is purely declarative — nothing in the IQ path reads it.
iq1_s_fake_quant dispatches straight to quantize_iq1_s, which reshapes with the module-level IQ1_S_BLOCK_SIZE = GGML_BLOCK_SIZE (modelopt/torch/quantization/ggml/common.py:22) and never consults quantizer.block_sizes. Likewise, TensorQuantizer._fake_quantize short-circuits into the backend entrypoint before the block_sizes/amax branches are reached (modelopt/torch/quantization/nn/modules/tensor_quantizer.py:891-896).
Why it matters: effective_bits right above got a "Keep in sync with IQ1_S_BLOCK_BYTES" note, but the 256 here has no such marker even though it is the same class of duplicated constant. Someone editing this to 128 (a reasonable-looking knob) would see no behavior change at all — the kernel would still pack 256-value super-blocks — which is a confusing silent no-op rather than an error.
Suggestion: add a one-line comment mirroring the effective_bits note, e.g. # Declarative only: the GGML kernel hardcodes GGML_BLOCK_SIZE. Keep in sync. Same applies to iq2_xs.yaml:10-11.
| | `iq1_s` | IQ1_S W1A16, all linears | none | GGML IQ auto search (no calibration) | | ||
| | `iq2_xs` | IQ2_XS W2A16, all linears | none | GGML IQ auto search (no calibration) | |
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[SUGGESTION] W1A16 / W2A16 understate the real storage cost, which is the number users compare against the neighbouring rows.
IQ1_S is 1.5625 bpw and IQ2_XS is 2.3125 bpw (the effective_bits values this PR adds in configs/numerics/iq*.yaml, matching IQ1_S_BLOCK_BYTES = 50 / IQ2_XS_BLOCK_BYTES = 74 over a 256-value super-block). The other rows in this table — INT4 W4A16, block 128, NVFP4 W4A16 (block 32) — are exact for their formats, so a reader scanning this column will read "W1A16" as 1 bpw and conclude IQ1_S is 4× smaller than INT4 when it is really ~2.6×.
Suggestion: put the effective bpw in the cell so the column stays comparable:
| | `iq1_s` | IQ1_S W1A16, all linears | none | GGML IQ auto search (no calibration) | | |
| | `iq2_xs` | IQ2_XS W2A16, all linears | none | GGML IQ auto search (no calibration) | | |
| | `iq1_s` | IQ1_S W1A16 (1.5625 bpw, block 256), all linears | none | GGML IQ auto search (no calibration) | | |
| | `iq2_xs` | IQ2_XS W2A16 (2.3125 bpw, block 256), all linears | none | GGML IQ auto search (no calibration) | |
| - **`iq1_s` / `iq2_xs`** — GGML-compatible IQ1_S or IQ2_XS weights on all linear | ||
| layers, with BF16 activations. No calibration data is required. Quantized weights must have a | ||
| final dimension divisible by 256. These recipes configure simulated weight quantization only; | ||
| packed checkpoint export is added separately. |
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[SUGGESTION] Two small precision gaps in this bullet, both worth closing because the 256 constraint is the main foot-gun for these two recipes.
-
"all linear layers" isn't quite what the preset does.
configs/ptq/presets/model/iq1_s.yamlimportsdefault_disabled_quantizers, solm_head/output_layer, MoE routers/gates, Mambaconv1d, and the whole vision branch stay in BF16. The recipe's ownmetadata.descriptionsays "eligible linear layers", which is accurate — worth matching that wording here. -
When the 256 check fires is not obvious.
validate_weight(modelopt/torch/quantization/ggml/common.py:29) raises on the first weight fake-quant. But these recipes setalgorithm:to null, so there is no calibration forward pass — nothing touches the weight quantizers duringmtq.quantize. TheValueErrortherefore surfaces at the first real model forward (eval, or export), well after the user believes quantization succeeded. On a model like Qwen2-0.5B (hidden 896,896 % 256 == 128) that is a confusing late failure.
Suggestion — reword along these lines, and consider a shape precheck at quantize time in a follow-up:
- **`iq1_s` / `iq2_xs`** — GGML-compatible IQ1_S (1.5625 bpw) or IQ2_XS (2.3125 bpw)
weights on eligible linear layers, with BF16 activations. No calibration data is
required. Every quantized weight must have a final dimension divisible by 256;
because these recipes run no calibration forward pass, a non-conforming layer is
only rejected at the first model forward, not during `mtq.quantize`. These recipes
configure simulated weight quantization only; packed checkpoint export is added
separately.
| # SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. | ||
| # SPDX-License-Identifier: Apache-2.0 |
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[SUGGESTION] All six new YAML files carry only the two-line SPDX header, while every other recipe YAML in the tree (configs/numerics/mxfp4.yaml, configs/numerics/nvfp4_four_over_six.yaml, configs/ptq/units/w4_nvfp4.yaml, general/ptq/mxfp4_mlp_weight_only.yaml, …) carries the full 14-line Apache 2.0 block from LICENSE_HEADER.
This won't be caught by CI: .pre-commit-config.yaml scopes insert-license to types_or: [python, shell] and to c/c++/cuda, so YAML is unchecked and the drift is permanent once merged. Worth appending the standard block for consistency with the rest of modelopt_recipes/.
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Claude review — [OMNIML-5899] Add IQ post-training quantization recipes
Scope reviewed: all 7 changed files (105 additions / 1 deletion). The PR is recipes-only, so the review traced each new YAML through the schema and runtime paths it feeds on the base branch (hungyuehc/omniml-5899-kernel-v2): QuantizerAttributeConfig / QuantizeConfig validation, TensorQuantizer backend dispatch, estimate_quant_compression, the GGML IQ kernels, and the tests/unit/recipe/ doc-consistency checks. I could not execute the test suite in this environment, so the test-level conclusions below come from reading the assertions, not from a run.
Findings
- CRITICAL: 0
- IMPORTANT: 0
- SUGGESTION: 4
| # | File | Finding |
|---|---|---|
| 1 | configs/numerics/iq1_s.yaml (+ iq2_xs) |
block_sizes: {-1: 256} is declarative only — the IQ backend hardcodes GGML_BLOCK_SIZE, so editing it is a silent no-op. Add a sync comment like the one effective_bits already has. |
| 2 | ptq.md:60-61 |
W1A16 / W2A16 understate real cost (1.5625 / 2.3125 bpw) versus the exact neighbouring rows. |
| 3 | ptq.md:140-143 |
"all linear layers" overstates the preset (default_disabled_quantizers exempts lm_head, routers, conv1d, vision); and with algorithm: null there is no calibration forward, so the 256-divisibility ValueError lands at the first real forward rather than at mtq.quantize. |
| 4 | new YAML headers | Two-line SPDX header vs. the full Apache block every other recipe YAML uses; insert-license is scoped to python/shell/c so CI will not catch the drift. |
What checked out
The recipe wiring is careful and closely follows existing precedent — several things that could plausibly have been wrong are correct here:
num_bitsas a string validates.QuantizerAttributeConfig.validate_num_bitsis amode="after"model validator that returns early whenbackend is not None, sonum_bits: iq1_s+backend: ggmlpasses. The backend name matchesregister_quant_backend("ggml", ...), andmodelopt/torch/quantization/__init__.py:32imports the module eagerly (_import_moduleisimportlib.import_module), so the registration is in place before any recipe loads — no plugin-laziness gap.effective_bitsis load-bearing, not decorative.estimate_quant_compression_for_quantizerraisesValueError: Unknown quantization configon a stringnum_bitsunlesseffective_bitsshort-circuits first, so declaring it in the numerics config is exactly what is required. Placing it there (rather than atQuantizeConfiglevel) matches theconfigs/numerics/nvfp4.yamlprecedent, and theminaggregation across entries picks it up past thebase_disable_all/ disabled entries.- Both bpw values are arithmetically right and agree with the kernel constants:
50 * 8 / 256 = 1.5625(IQ1_S_BLOCK_BYTES),74 * 8 / 256 = 2.3125(IQ2_XS_BLOCK_BYTES) — also matchingconvert_hf_config.py:121and llama.cpp published figures. Both sit inside the(0, 16]validator range. algorithm:null is correct, not an omission. The backend entrypoint is dispatched at the top of_fake_quantize, ahead of every amax branch, so IQ genuinely needs no calibration — mirroring themxfp4_mlp_weight_onlyprecedent. The preset structure (base_disable_all->*weight_quantizercfg ->*input_quantizerdisabled ->default_disabled_quantizers) matchesint4_blockwise_weight_onlyexactly, and importing the numerics config implicitly re-enables viaenable: bool = True.mtq.compressfails loudly, not silently. Worth recording since it was my main suspicion: withnum_bits="iq1_s"and staticblock_sizes, the trailingelsein_real_quantizewould hand the weight toINT4QTensor.quantizeand produce plausible-looking INT4 weights. That path is unreachable —_is_real_quantize_support()returnsFalsefor a stringnum_bits, so the assert attensor_quantizer.py:797trips first. No landmine.- Doc-consistency tests should pass.
general/ptq/now holds 27 recipes, the summary line says 27, and the table has exactly 27 backticked rows with both new stems present — satisfying all three assertions intest_recipe_docs.py.test_shipped_ptq_recipe_algorithm_config_constructsis a no-op for a nullalgorithm. - Vision/MoE exclusions are inherited correctly via
default_disabled_quantizers, which matters here because*weight_quantizeris a bare wildcard.
One thing outside the diff
No CHANGELOG.rst entry exists for the IQ formats anywhere in this stack (checked at this commit, including the base branch). Per CLAUDE.md new features warrant one — presumably intended for PR 5 of 5, but flagging it so it does not fall through the stack.
Risk
Low. Additive, data-only change: six new YAML files plus a doc table row, no source or schema modification, no existing recipe or modelopt_state key touched, so there is no backward-compatibility or restore-fidelity surface. The one real user-facing sharp edge — the 256-divisibility requirement — is documented and enforced by an explicit raise with a clear message; only the timing of that error is worth improving (finding 3). All four findings are documentation and comment polish; none blocks merge.
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Signed-off-by: Hung-Yueh Chiang <hungyuehc@nvidia.com>
Signed-off-by: Hung-Yueh Chiang <hungyuehc@nvidia.com>
Signed-off-by: Hung-Yueh Chiang <hungyuehc@nvidia.com>
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| | `iq1_s` | IQ1_S W1A16, all linears | none | GGML IQ auto search (no calibration) | | ||
| | `iq2_xs` | IQ2_XS W2A16, all linears | none | GGML IQ auto search (no calibration) | |
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[SUGGESTION] The Calibration column advertises a step that does not exist.
Both recipes set algorithm: (null) in configs/ptq/presets/model/iq{1_s,2_xs}.yaml, so mtq.quantize performs no calibration pass at all — exactly like mxfp4_mlp_weight_only on line 60, whose cell reads none (no calibration). The codebook lookup that "GGML IQ auto search" refers to happens inside the ggml backend entrypoint on every _fake_quantize call, per weight block; it is neither a calibration pass nor a recipe-level search, and this column describes the former. The latest commit on this branch (d658c5f2, "Remove unused IQ search recipe option") removed the only recipe knob that could have justified the word "search", so the doc now names a mechanism the recipe deliberately does not have.
Why it matters: this column is what users scan to decide whether they need to supply a calibration dataset and to budget calibration time. A non-empty entry here reads as "something runs at quantize time", which will send people looking for a --calib-* flag or an algorithm to tune. Aligning the wording with the mxfp4_mlp_weight_only row keeps the table's vocabulary consistent.
| | `iq1_s` | IQ1_S W1A16, all linears | none | GGML IQ auto search (no calibration) | | |
| | `iq2_xs` | IQ2_XS W2A16, all linears | none | GGML IQ auto search (no calibration) | | |
| | `iq1_s` | IQ1_S W1A16, all linears | none | none (no calibration) | | |
| | `iq2_xs` | IQ2_XS W2A16, all linears | none | none (no calibration) | |
| final dimension divisible by 256. These recipes configure simulated weight quantization only; | ||
| packed checkpoint export is added separately. |
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[SUGGESTION] "packed checkpoint export is added separately" will be stale the moment this merges.
The PR description pins the merge order as #2448 → #2446 → #2447 (Export IQ checkpoints from HF and Megatron) → #2449. Since export lands before this PR, the sentence describes a gap that no longer exists at the time a user reads it. Phrasing that points forward to unmerged work is fine on a stacked branch but does not survive the merge — and unlike the recipe count, no test catches this drift, so it will sit in ptq.md indefinitely.
Why it matters: users reading "simulated weight quantization only" will reasonably conclude they cannot get a deployable IQ checkpoint out of these recipes and will stop there, even though export_hf_checkpoint supports it once #2447 is in.
Suggest either dropping the clause, or replacing it with a pointer to the export path — e.g.:
- **`iq1_s` / `iq2_xs`** — GGML-compatible IQ1_S or IQ2_XS weights on all linear
layers eligible after `default_disabled_quantizers`, with BF16 activations. No
calibration data is required. Quantized weights must have a final dimension
divisible by 256.
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Claude review — [OMNIML-5899] Add IQ post-training quantization recipes
Scope reviewed: all 8 changed files (102 additions / 1 deletion). Recipes-only PR, so the review traced each new YAML through the schema and runtime paths it feeds — QuantizerAttributeConfig / QuantizeConfig validation, TensorQuantizer backend dispatch, estimate_quant_compression, and the tests/unit/recipe/ doc-consistency assertions.
This is a re-review of an earlier pass (commit 7f977a2). Two things changed materially since then, and both were re-verified from scratch: the base branch moved from hungyuehc/omniml-5899-kernel-v2 to main, and the search: recipe option was removed. I was not able to execute pytest in this environment, so the test-level conclusions below come from reading the assertions, not from a run.
Findings (this round)
- CRITICAL: 0
- IMPORTANT: 0
- SUGGESTION: 2
| # | File | Finding |
|---|---|---|
| 1 | ptq.md:61-62 |
Calibration column says GGML IQ auto search (no calibration), but algorithm: is null and the codebook lookup lives inside the backend per-block fake-quant — not a calibration pass. d658c5f2 removed the only knob the word "search" could refer to. Suggest none (no calibration), matching the mxfp4_mlp_weight_only row. |
| 2 | ptq.md:143-144 |
"packed checkpoint export is added separately" is stale on arrival — the declared merge order puts #2447 (export) before this PR. No test catches this drift. |
Re-verified after the base-branch move to main
This was the main new risk, since main has no IQ codec yet — grep -rln "iq1_s|IQ1_S" modelopt/ returns nothing at this commit. Result: the stacking is safe in both directions.
- Recipes still load on
main.QuantizerAttributeConfig.validate_num_bits(config.py:391-395) returns early whenbackend is not None, sonum_bits: iq1_s+backend: ggmlvalidates without the codec present.backendis a plainstr | Nonefield with no registry check at config time, sotest_load_recipe_all_builtins— which discovers recipes from disk and so picks up both new files — stays green pre-#2446. - An unregistered backend fails loudly, not silently.
tensor_quantizer.py:892-894raisesKeyError: Quant backend 'ggml' is not registered.before any amax branch. Worth recording explicitly: had that lookup fallen through, a staticblock_sizes: {-1: 256}with a stringnum_bitswould have produced plausible-looking-but-wrong weights. It cannot. - Recipe count test passes.
general/ptq/now holds exactly 28*.yaml; the summary line says 28 and both stems are backticked in the table, satisfying all three assertions intest_recipe_docs.py. - CHANGELOG entry is correctly placed and scoped. Under
0.48.0 (2026-10-xx)→**New Features**→*Quantization*— an existing sub-section, not a relabeled one — one sentence, user-facing, no internal bug IDs. This closes the gap flagged last round, where no entry existed anywhere in the four-PR stack. - Preset structure matches precedent exactly.
base_disable_all→*weight_quantizercfg →*input_quantizerdisabled →default_disabled_quantizersis the same shape asint4_blockwise_weight_only;algorithm:null matchesmxfp4_mlp_weight_only. The bare*weight_quantizerwildcard is safe becausedefault_disabled_quantizersexemptslm_head, routers, MoE gates,conv1d,nn.Embedding, and the whole vision branch — the last of which matters here for the same reason cited in that unit for NVFP4 (patch_embedding.linearwithin_features=588is not block-divisible either). effective_bitsis load-bearing.estimate_quant_compression_for_quantizerraises on a stringnum_bitsunlesseffective_bitsshort-circuits, so declaring it in the numerics config is required, not decorative. Both values are arithmetically right (50*8/256 = 1.5625,74*8/256 = 2.3125) and inside the(0, 16]validator range.
Prior-round suggestions still open
Non-blocking, but noting them so they do not get lost: the block_sizes: {-1: 256} declarative-no-op comment, the W1A16 / W2A16 cells understating real cost (1.5625 / 2.3125 bpw) next to exact neighbouring rows, "all linear layers" overstating what the preset actually quantizes, and the two-line SPDX header where every neighbouring recipe YAML (configs/numerics/nvfp4.yaml, mxfp4.yaml, both comparable presets) carries the full Apache block — insert-license is scoped to python/shell/c, so CI will not flag the drift.
Risk
Low. Additive, data-only: six new YAML files, one doc table row pair, one changelog line. No source, schema, or modelopt_state key touched, so there is no restore-fidelity or checkpoint-compatibility surface. The one real user-facing sharp edge — 256-divisibility of the last weight dimension — is documented and enforced by an explicit raise. Both findings are doc accuracy; neither blocks merge. The stated merge order (#2448 → #2446 → #2447 → #2449) should still be honoured, but a premature merge degrades to a clear KeyError rather than silent miscompute.
Approving — no blocking issues found.
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Inline comments:
In `@modelopt_recipes/ptq.md`:
- Around line 141-144: Update the documentation heading around the iq1_s and
iq2_xs recipe entries to use a generic weight-only-format description rather
than classifying them as W4A16. Keep the existing recipe details unchanged and
ensure the heading accurately covers both W1A16 and W2A16 schemes.
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CHANGELOG.rstmodelopt_recipes/configs/numerics/iq1_s.yamlmodelopt_recipes/configs/numerics/iq2_xs.yamlmodelopt_recipes/configs/ptq/presets/model/iq1_s.yamlmodelopt_recipes/configs/ptq/presets/model/iq2_xs.yamlmodelopt_recipes/general/ptq/iq1_s.yamlmodelopt_recipes/general/ptq/iq2_xs.yamlmodelopt_recipes/ptq.md
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| - **`iq1_s` / `iq2_xs`** — GGML-compatible IQ1_S or IQ2_XS weights on all linear | ||
| layers, with BF16 activations. No calibration data is required. Quantized weights must have a | ||
| final dimension divisible by 256. These recipes configure simulated weight quantization only; | ||
| packed checkpoint export is added separately. |
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🎯 Functional Correctness | 🟡 Minor | ⚡ Quick win
Use a generic heading for all weight-only formats.
The added recipes are W1A16 and W2A16, but they appear under Weight-only schemes (W4A16 — activations stay BF16). Rename that heading or place the IQ entries in a separate section so the documentation does not classify them as W4A16.
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In `@modelopt_recipes/ptq.md` around lines 141 - 144, Update the documentation
heading around the iq1_s and iq2_xs recipe entries to use a generic
weight-only-format description rather than classifying them as W4A16. Keep the
existing recipe details unchanged and ensure the heading accurately covers both
W1A16 and W2A16 schemes.
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## Summary - add native CUDA packing kernels for IQ1_S and IQ2_XS - load both extensions through the quantization extension module - validate caller metadata and launch bounds before contiguous materialization - normalize non-finite input elements consistently with the Python reference path - accept caller-computed IQ2_XS FP16 superblock scales to avoid a duplicate reduction - share common packing helpers and add direct extension compilation and boundary tests ## PR split This work is split into four focused PRs. Each PR targets `main` and owns a disjoint file set: 1. **Kernel** — [#2448: Add CUDA kernels for IQ packing](#2448) 2. **Quantization** — [#2446: Add IQ quantization codecs and backend](#2446) 3. **Export** — [#2447: Export IQ checkpoints from HF and Megatron](#2447) 4. **Recipes** — [#2449: Add IQ post-training quantization recipes](#2449) The required merge order is #2448, #2446, #2447, then #2449. ## Scope This PR owns only native kernel sources, shared packing helpers, extension loading and build registration, and direct extension tests. It does not contain Python codecs, export code, or recipes. ## GPU test coverage Direct kernel-boundary coverage is included in this PR: - [extension compilation, zero payloads, input validation, and row-alignment checks](https://github.com/NVIDIA/Model-Optimizer/blob/74e94db9601870e3569c7c8e73506a2f08c29da8/tests/gpu/_extensions/test_torch_extensions.py) Pack/dequantize numerical, native/reference byte-parity, and non-finite-policy tests are owned by the quantization PR: [IQ1_S](https://github.com/NVIDIA/Model-Optimizer/blob/e8d937081d8cd01cf8e44d43915df443b79deb17/tests/gpu/torch/quantization/test_iq1_s_cuda.py) and [IQ2_XS](https://github.com/NVIDIA/Model-Optimizer/blob/e8d937081d8cd01cf8e44d43915df443b79deb17/tests/gpu/torch/quantization/test_iq2_xs_cuda.py). ## Dependency behavior On `main`, this PR provides optional CUDA extension loaders and direct extension tests. The Python encoders and fallback dispatch land in #2446. Until #2446 lands, no quantization path calls these getters, so a load failure reports only that the extension is unavailable. The IQ2_XS packer accepts one caller-computed FP16 scale per 256-value block. #2446 owns that predictor and passes the same values to the native and reference encoders. ## Provenance - The CUDA kernels were independently written. - They implement the packed-format contract and sign-parity convention from the pinned [llama.cpp definition](https://github.com/ggml-org/llama.cpp/blob/9b05354ec6fb58b4e665e9a39ebc40285c015638/ggml/src/ggml-common.h). - `16.875 = 15 × (1 + 1/8)` is a derived IQ1_S constant. - `0.125` is part of the encoded format. - `0.61` is our empirical IQ1_S scale predictor, not copied from upstream code. - The IQ2_XS predictor constants are owned by #2446 and are not duplicated in this kernel. Human review is still required to confirm that the attribution and license treatment are sufficient. ## Validation - repository hooks, including native formatting, pass for all changed files - extension loader and test modules compile as Python - all 20 direct-extension and CUDA integration test cases collect locally - CUDA runtime execution is delegated to GPU CI because the local host is macOS - restricted-term scan passes --------- Signed-off-by: Hung-Yueh Chiang <hungyuehc@nvidia.com> Signed-off-by: Chenjie Luo <chenjiel@nvidia.com> Co-authored-by: Chenjie Luo <chenjiel@nvidia.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
### What does this PR do? Type of change: Code refactoring `#2448` added the GGML IQ packing kernels as **two** torch extensions, `modelopt_cuda_ext_iq1_s` and `modelopt_cuda_ext_iq2_xs`. This merges them into one, `modelopt_cuda_ext_ggml`. The existing per-extension split in `extensions.py` exists for reasons that don't apply to the IQ formats: `get_cuda_ext` gates on CUDA `>=11` while `_fp8`/`_mx` gate on `>=11.8`, and `_mx` needs `--use_fast_math`, which must not reach the base `tensor_quant` kernels. `get_cuda_ext_iq1_s` and `get_cuda_ext_iq2_xs` differed in none of that — same `>=11.8` gate, same `-O3` flags, same `common.cuh` — so the split only compiled the shared header twice, ran nvcc twice, and grew the loader, `__getattr__`, and `precompile()` once per format. With IQ2_XXS / IQ3_S / IQ4_NL plausibly following, that scales badly. Changes: - New `ggml/ggml.cpp` holds both host-side validation wrappers and the single `PYBIND11_MODULE`, binding `iq1_s_pack` and `iq2_xs_pack` (previously each module exported a bare `pack`). Deletes `ggml/iq1_s.cpp` and `ggml/iq2_xs.cpp`; the validation logic and docstrings carry over unchanged. - `get_cuda_ext_iq1_s` + `get_cuda_ext_iq2_xs` → `get_cuda_ext_ggml`, which builds `ggml.cpp`, `iq1_s.cu`, and `iq2_xs.cu` together. The retry-on-`raise_if_failed` semantics of the old getters are preserved. - Each format keeps its kernels in its own translation unit, so adding a format is a new `.cu` plus one `module.def` — no new extension, loader, or `precompile()` line. No caller outside `extensions.py` and its tests referenced the old getters on `main`, so nothing else changes. **Note for the follow-up PRs in the `#2448` series (`#2446`/`#2447`/`#2449`): the codec layer should call `get_cuda_ext_ggml().iq1_s_pack(...)` / `.iq2_xs_pack(...)` instead of `get_cuda_ext_iq1_s().pack(...)` / `get_cuda_ext_iq2_xs().pack(...)`.** ### Usage ```python from modelopt.torch.quantization.extensions import get_cuda_ext_ggml ext = get_cuda_ext_ggml(raise_if_failed=True) iq1_s_payload = ext.iq1_s_pack(weight, iq1s_grid) # uint8 [numel / 256, 50] iq2_xs_payload = ext.iq2_xs_pack(weight, iq2xs_grid, scales) # uint8 [numel / 256, 74] ``` ### Testing Ran on a single H200 NVL (TRT-LLM `1.3.0rc27.dev202609170000` container), building the merged extension from scratch: - `pytest tests/gpu/_extensions/test_torch_extensions.py` — **24 passed** (6:44). This is the full existing IQ suite (zero-block layout, encode, dtype rejection, row-straddling rejection, invalid/negative-zero scales, byte-exact dtype equivalence, and the brute-force optimality round-trip) reparametrized onto the merged module, plus the untouched `modelopt_cuda_ext` / `_fp8` / `_mx` load tests. - Verified `precompile()` loads all four extensions and that the merged module exports exactly `iq1_s_pack` and `iq2_xs_pack` with the expected arities. - Off-GPU: compiled the three sources directly and linked them into one `.so` to confirm no duplicate-symbol collisions between the two `.cu` translation units. - `pre-commit run --files ...` passes on all changed files (ruff, mypy, clang-format, bandit, license headers). ### Before your PR is "*Ready for review*" - Is this change backward compatible?: ✅ — the removed getters were added in `#2448` (merged today, unreleased) and have no callers outside this file's own tests. - If you copied code from any other sources or added a new PIP dependency, did you follow guidance in `CONTRIBUTING.md`: N/A — no new code or dependencies; the moved wrappers keep their original attribution. - Did you write any new necessary tests?: ✅ — existing coverage reparametrized onto the merged module; no behavior change to test. - Did you update [Changelog](https://github.com/NVIDIA/Model-Optimizer/blob/main/CHANGELOG.rst)?: N/A — internal refactor of an unreleased, not-yet-wired-up API. - Did you get Claude approval on this PR?: ❌ — not yet run. ### Additional Information Follow-up to #2448. Merge before the remaining PRs in that series (#2446, #2447, #2449) land, so the codec layer is written against `get_cuda_ext_ggml` and no rename is needed afterwards. 🤖 Generated with [Claude Code](https://claude.com/claude-code) <!-- This is an auto-generated comment: release notes by coderabbit.ai --> ## Summary by CodeRabbit - **New Features** - Added IQ1_S packing support through the GGML CUDA extension. - Added a unified GGML extension loader for IQ1_S and IQ2_XS packing. - Improved extension loading reliability when a cached extension is unavailable. - **Changes** - Renamed the IQ2_XS packing binding from `pack` to `iq2_xs_pack`. - Consolidated IQ1_S and IQ2_XS extension access under the shared GGML loader. - Updated GPU validation and coverage to use the unified extension interface. <!-- end of auto-generated comment: release notes by coderabbit.ai --> Signed-off-by: Chenjie Luo <chenjiel@nvidia.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
## Summary - add IQ1_S and IQ2_XS reference codecs and a weight-only fake-quant backend - register and export both formats from the quantization package - cache compact packed weights across unchanged forwards and invalidate on tensor or config changes - use one Python-side IQ2_XS FP16 scale predictor for both reference and CUDA packing - validate packed payload metadata, normalize CUDA cache keys, and define a shared non-finite policy ## PR split This work is split into four focused PRs. Each PR targets `main` and owns a disjoint file set: 1. **Kernel** — [#2448: Add CUDA kernels for IQ packing](#2448) 2. **Quantization** — [#2446: Add IQ quantization codecs and backend](#2446) 3. **Export** — [#2447: Export IQ checkpoints from HF and Megatron](#2447) 4. **Recipes** — [#2449: Add IQ post-training quantization recipes](#2449) The required merge order is #2448, #2446, #2447, then #2449. ## Scope This PR owns the Python codecs, backend dispatch, package registration, license attribution, CPU codec/backend tests, and CUDA numerical/reference-path tests. The native CUDA layer and direct extension tests remain in #2448; export and recipes remain in their own PRs. ## Why the codecs are separate from `qtensor` The new `ggml/` package contains stateless reference codecs and fake-quant backend functions. They transform ordinary tensors into packed format payloads and reconstruct tensors for fake quantization; they do not define persistent runtime quantized-tensor objects. `BaseQuantizedTensor` subclasses under `qtensor/` own runtime tensor objects and execution dispatch. Keeping the codecs separate avoids claiming a runtime tensor contract that these formats do not yet provide. A `qtensor` type can be added later if a runtime execution path requires one. ## Compatibility boundary The Python encoders intentionally use fixed-scale, unweighted searches. They are not intended to reproduce another encoder's bytes for every input when that encoder performs iterative scale refinement or importance weighting. Compatibility is defined by the canonical codebooks, 50/74-byte payload layouts, and pinned dequantization formulas. IQ2_XS computes the FP16 superblock scale once in the Python predictor and passes it to the CUDA packer. This removes a duplicate floating-point reduction and makes native/reference byte parity use the same scale. Non-finite input elements are treated as zero during packing in both implementations. The unit tests construct nonzero payload fields independently and validate metadata, signs, local scales, and global scales. The CUDA tests compare native packed bytes with this Python reference encoder. ## Test coverage - [IQ1_S CPU codec tests](https://github.com/NVIDIA/Model-Optimizer/blob/e8d937081d8cd01cf8e44d43915df443b79deb17/tests/unit/torch/quantization/test_iq1_s.py) - [IQ2_XS CPU codec tests](https://github.com/NVIDIA/Model-Optimizer/blob/e8d937081d8cd01cf8e44d43915df443b79deb17/tests/unit/torch/quantization/test_iq2_xs.py) - [registered backend and cache tests](https://github.com/NVIDIA/Model-Optimizer/blob/e8d937081d8cd01cf8e44d43915df443b79deb17/tests/unit/torch/quantization/test_ggml_backend.py) - [IQ1_S CUDA byte-parity, numerical, non-finite, zero-payload, and fallback tests](https://github.com/NVIDIA/Model-Optimizer/blob/e8d937081d8cd01cf8e44d43915df443b79deb17/tests/gpu/torch/quantization/test_iq1_s_cuda.py) - [IQ2_XS CUDA byte-parity, numerical, non-finite, zero-payload, underflow, and fallback tests](https://github.com/NVIDIA/Model-Optimizer/blob/e8d937081d8cd01cf8e44d43915df443b79deb17/tests/gpu/torch/quantization/test_iq2_xs_cuda.py) ## Licensing The embedded codebook data cites the pinned upstream MIT source, carries its license notice, and uses the repository's third-party license mechanism. Human OSRB/code-owner confirmation is still required; this PR does not claim that approval. ## Validation - focused lint, format, and type checks pass for all changed Python files - 36 focused CPU codec and backend tests pass locally - all 20 direct-extension and CUDA integration test cases collect locally; runtime CUDA execution remains delegated to GPU CI - restricted-term scan passes <!-- This is an auto-generated comment: release notes by coderabbit.ai --> ## Summary by CodeRabbit - **New Features** - Added GGML quantization support for IQ1_S and IQ2_XS formats. - Added quantization, dequantization, and fake-quantization workflows with pass-through gradients. - Added CPU fallback when CUDA acceleration is unavailable. - Added validation for packed weights, tensor shapes, formats, and backend options. - Added configurable chunk processing and caching for repeated quantization. - **Tests** - Added comprehensive CPU and CUDA coverage for accuracy, validation, caching, fallback behavior, and edge cases. <!-- end of auto-generated comment: release notes by coderabbit.ai --> --------- Signed-off-by: Hung-Yueh Chiang <hungyuehc@nvidia.com> Signed-off-by: Chenjie Luo <chenjiel@nvidia.com> Co-authored-by: Chenjie Luo <chenjiel@nvidia.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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Nudge: the recipes are correct and reuse the existing numerics/preset/$import system (no new abstraction, so the design gate is satisfied), but the new YAMLs drop the canonical license header and nothing pins the hand-computed effective_bits.
Needs action:
- Replace the two-line SPDX header in the four new YAMLs (
configs/numerics/iq{1_s,2_xs}.yaml,configs/ptq/presets/model/iq{1_s,2_xs}.yaml,general/ptq/iq{1_s,2_xs}.yaml) with the fullLICENSE_HEADERtext every sibling recipe YAML carries — or state that the short form is intentional. - Add a test asserting each shipped IQ recipe resolves to
backend: ggml,num_bits: iq1_s/iq2_xsandeffective_bits == IQ1_S_EFFECTIVE_BITS/IQ2_XS_EFFECTIVE_BITS; the "Keep in sync with IQ1_S_BLOCK_BYTES" comment is currently unenforced. - Confirm
block_sizes: {-1: 256}is actually consumed (the ggml backend derives its own super-block scale and ignoresblock_sizes) — say in the PR body which consumer reads it, e.g. the export path. - Confirm that landing the presets under
configs/ptq/presets/model/intentionally adds--qformat iq1_s/iq2_xstohf_ptq, given packed export only exists after #2447 merges.
No action needed:
- Shipped-recipe smoke tests (
tests/unit/recipe/test_loader.py,test_presets.py) auto-discover the new files, so load/schema validation is covered.
Codecov Report✅ All modified and coverable lines are covered by tests. Additional details and impacted files@@ Coverage Diff @@
## main #2449 +/- ##
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Coverage 70.74% 70.74%
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Files 601 601
Lines 66300 66300
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+ Hits 46906 46907 +1
+ Misses 19394 19393 -1
Flags with carried forward coverage won't be shown. Click here to find out more. ☔ View full report in Codecov by Harness. 🚀 New features to boost your workflow:
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Signed-off-by: Hung-Yueh Chiang <hungyuehc@nvidia.com>
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Addressed in
Validation: 360 recipe tests passed; recipe validation, formatting, lint, license, and the remaining changed-file pre-commit checks passed. |
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Approving: every concern from the last round is resolved in a2849c6f3, and the remaining open items are one-line doc polish already recorded by other reviewers.
No action needed:
- ✔️ Resolved since the last review: the four new YAMLs now carry the canonical
LICENSE_HEADERverbatim;test_iq_recipe_matches_packing_contractpinsbackend,num_bits,block_sizes[-1]andeffective_bitstoIQ*_BLOCK_SIZE/IQ*_EFFECTIVE_BITS; the PR body now names the export consumer ofblock_sizes[-1]and confirms the--qformat iq1_s/iq2_xsexposure is intentional behind the stated merge order. - Recipe count checks out —
general/ptq/holds 28 YAMLs andptq.mdsays 28. - Minor and non-blocking: in
ptq.md, the IQ rows sit under theW4A16weight-only heading and "packed checkpoint export is added separately" goes stale once #2447 lands ahead of this PR. Worth a one-line touch-up if you re-push.
Large PR: spans 5 directories (≥ 5). The review came back clean, so this is an LGTM — a human should take the final look and approve.
Testing: No test plan or testing section found in the PR description.
Suggested test plan:
- Run
tests/unit/recipe/test_presets.py(especially the newtest_iq_recipe_matches_packing_contractparametrization) and confirm the importedIQ*_BLOCK_SIZE/IQ*_EFFECTIVE_BITSconstants exist and match the YAML values (1.5625 / 2.3125, block 256) — verify the test fails if a YAML value is edited. - Load
general/ptq/iq1_sandiq2_xsand validate the resolvedQuantizeConfigagainst the schema: weight quantizer enabled withbackend: ggml, input/output quantizers disabled,algorithm: null(no calibration), and no unused/ignored search or scale-search keys. - Do a short end-to-end
mtq.quantizesmoke run on a tiny model with each recipe (no calib data) and confirm weights are fake-quantized,TensorQuantizer.block_sizes[-1] == 256, and outputs are finite/deterministic. - Confirm the documented shape constraint: a linear whose last dim is not divisible by 256 raises a clear error (or is excluded), and one divisible by 256 quantizes successfully.
- Verify the
--qformat iq1_s/iq2_xschoices are actually registered inpresets.QUANT_CFG_CHOICES/hf_ptqand thathf_ptqruns at least to the quantize
## Summary - add IQ format metadata and packed-weight export - support Hugging Face and TP=1 Megatron export paths - reject fused-MoE IQ export until a deployment loader owns its packed layout - document the shaped `uint8` weight contract and the fused-expert boundary - add Hugging Face, Megatron, metadata, and fused-expert export tests ## PR split This work is split into four focused PRs. Each PR targets `main` and owns a disjoint file set: 1. **Kernel** — [#2448: Add CUDA kernels for IQ packing](#2448) 2. **Quantization** — [#2446: Add IQ quantization codecs and backend](#2446) 3. **Export** — [#2447: Export IQ checkpoints from HF and Megatron](#2447) 4. **Recipes** — [#2449: Add IQ post-training quantization recipes](#2449) The required merge order is #2448, #2446, #2447, then #2449. ## Scope This PR owns only export code, deployment documentation, and export tests. It targets `main` and should merge after #2448 and #2446. It does not contain kernel, codec/backend, or recipe files. ## Deployment consumer boundary Dense weights and individually named expert weights use the documented shaped `uint8` contract. Megatron fused-MoE IQ export is intentionally rejected with `NotImplementedError`: its payload would have shape `[num_experts, out_features, in_features // 256, payload_bytes]`, and no deployment loader in this stack currently owns that layout. Support should be enabled only with a loader integration test. ## Test coverage - [Hugging Face packed-weight export](https://github.com/NVIDIA/Model-Optimizer/blob/11cd58d907465933f5a552bc1a8065f84c9ba3b1/tests/unit/torch/export/test_export_weight.py) - [quantization metadata](https://github.com/NVIDIA/Model-Optimizer/blob/11cd58d907465933f5a552bc1a8065f84c9ba3b1/tests/unit/torch/export/test_get_quantization.py) - [Megatron unified export and fused-MoE rejection](https://github.com/NVIDIA/Model-Optimizer/blob/11cd58d907465933f5a552bc1a8065f84c9ba3b1/tests/gpu_megatron/torch/export/test_unified_export_megatron.py) ## Validation - all pre-commit hooks pass for the changed files - 89 focused Hugging Face export, metadata, and fused-expert tests pass locally - direct checks cover both fused-MoE export entry points for IQ1_S and IQ2_XS - Megatron GPU execution remains delegated to GPU CI - restricted-term scan passes <!-- This is an auto-generated comment: release notes by coderabbit.ai --> ## Summary by CodeRabbit * **New Features** * Added support for IQ1_S and IQ2_XS GGML quantization formats in unified Hugging Face and Megatron exports. * Added quantization metadata, tensor-shape recovery, packing details, and IQ2_XS size documentation. * Added validation for required block sizes and tensor parallelism settings. * **Limitations** * Fused-MoE and GPT-OSS IQ expert packing are not supported. * IQ exports require standard `weight` attributes in Hugging Face models. <!-- end of auto-generated comment: release notes by coderabbit.ai --> --------- Signed-off-by: Hung-Yueh Chiang <hungyuehc@nvidia.com> Signed-off-by: Chenjie Luo <chenjiel@nvidia.com> Co-authored-by: Chenjie Luo <chenjiel@nvidia.com> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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Summary
PR split
This work is split into four focused PRs. Each PR targets
mainand owns a disjoint file set:The required merge order is #2448, #2446, #2447, then #2449.
Scope
This PR targets
mainand owns only eight recipe configuration, recipe documentation, and changelog files. It should merge after the kernel, quantization, and export PRs. It does not contain kernel, codec/backend, or export files.Integration contracts
block_sizes: {-1: 256}records the native packed-block contract; it does not drive the GGML fake-quant scale search. After [OMNIML-5899] Export IQ checkpoints from HF and Megatron #2447 lands, the export path readsTensorQuantizer.block_sizes[-1]throughget_weight_block_size, validates it against the format block size, and recordsgroup_size: 256in checkpoint metadata.--qformat iq1_sand--qformat iq2_xsinhf_ptq. This PR remains last in the merge order so those choices land only after [OMNIML-5899] Export IQ checkpoints from HF and Megatron #2447 provides packed-checkpoint export.Validation
Summary by CodeRabbit
New Features
Documentation