Refactor MMFF CUDA kernels for typed instantiation

[scal444]

Summary

• refactor the shared MMFF CUDA implementation and launch internals to use a scalar template
• instantiate and expose only the existing FP64 path in this PR
• preserve current behavior and public interfaces
• prepare a clean instantiation point for FP32 support in the next PR

This is PR 1 of the mixed-precision minimizer stack.

[greptile-apps]

Confidence Score: 5/5

The PR appears safe to merge within its clarified scope as a behavior-preserving FP64 typed-instantiation refactor.

Findings

1.  Float MMFF Path Removed ▶
2.  Float Path Lacks Tests ▶

Summary

• Templates MMFF contribution-pointer structures while retaining compatibility aliases for existing types.
• Moves shared device implementation instantiation into an FP64 dispatch header.
• Generalizes combined energy and gradient launch internals, but emits only the existing double-precision launchers.
• Updates MMFF consumers to include the new dispatch header.

_{Reviews (3) · Last reviewed commit: "Refactor MMFF CUDA kernels for typed ins..."}

[scal444]

#266 PR 1

[evasnow1992]

Changes look good to me.