32-bit High-Performance ALU & Single-Cycle RISC Processor

A 32-bit single-cycle RISC processor design implemented in Verilog HDL, featured around an optimized, high-speed Arithmetic Logic Unit (ALU). The design combines parallel-prefix adders, Booth-encoded Dadda multipliers, combinational dividers, and barrel shifters for single-cycle operation.

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🏛️ System Architecture Overview

The single-cycle SimpleRISC processor executes one instruction per clock cycle using a purely combinational data path and control unit.

                    +------------------------------------+
                    |        Instruction Memory          |
                    +-----------------+------------------+
                                      | [31:0] Instruction
                                      v
+------------------+         +------------------+         +------------------+
|   Program        |-------> |   Control Unit   |-------> | Immediate Unit   |
|   Counter (PC)   |         |   & Decoder      |         |     (IMMU)       |
+------------------+         +--------+---------+         +--------+---------+
                                      |                            |
                                      v                            v
                             +------------------+         +------------------+
                             |  Register File   |-------> | 32-bit High-Speed|
                             |  (16 Registers)  |         |     ALU Core     |
                             +------------------+         +--------+---------+
                                                                   | Result
                                                                   v
                                                          +------------------+
                                                          |   Data Memory    |
                                                          |     (DMEM)       |
                                                          +------------------+

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⚡ ALU Module & Algorithm Specifications

1. Adder & Subtractor (rtl/fast_adders.v)

• Algorithm: 32-bit Kogge-Stone Adder (KSA).
• Features: Parallel-prefix carry propagation reducing carry chain delay to $\mathcal{O}(\log_2 N)$.
• Subtraction: Evaluates $A - B = A + \sim B + 1$ using two's complement arithmetic within the same KSA topology.

2. Multi-Mode Barrel Shifter (rtl/shifter.v)

• Algorithm: Multi-stage log-barrel shifter ($2^0, 2^1, 2^2, 2^3, 2^4$ shift stages).
• Supported Operations:
  • 00: Logical Shift Left (LSL)
  • 01: Logical Shift Right (LSR)
  • 10: Arithmetic Shift Right (ASR) - preserves sign bit

3. Signed Multiplier (rtl/multiplier.v, rtl/encoder.v, rtl/tree_reducer.v)

• Algorithm: Radix-4 Booth Encoding + Dadda Tree Reduction + 64-bit Kogge-Stone Adder.
• Stage 1: Radix-4 Booth encoder compresses $32 \times 32$ multiplication into 16 partial products of 64-bit width.
• Stage 2: Dadda reduction tree compresses 16 partial product vectors down to 2 vectors (sum and carry).
• Stage 3: 64-bit Kogge-Stone adder computes final product.

4. Combinational Divider (rtl/divider.v)

• Algorithm: Single-cycle Non-Restoring Division algorithm.
• Features: Computes 32-bit signed Quotient and Remainder without iterative sequential state machines.

5. Set Less Than & Bitwise Logic (rtl/slt.v, rtl/alu.v)

• SLT Unit: Evaluates signed comparison $A < B$ using difference sign and overflow flags.
• Logic Unit: Purely combinational bitwise AND, OR, XOR, NOR, and NOT operations.

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📊 Design Trade-offs & Synthesis Analysis

Single-Cycle $\le 4\text{ns}$ Timing Constraint Analysis

• Observation: All ALU operations (Addition, Subtraction, Logic, Shift, Comparison, Multiplication) satisfy a $\le 4\text{ns}$ clock cycle timing target.
• Divider Bottleneck: The unrolled 32-bit non-restoring divider violates the 4ns timing constraint due to sequential algorithmic dependency.
• Root Cause: An $N$-bit non-restoring division unrolls into 32 cascaded subtract/compare/shift stages where each stage depends on the sign of the previous partial remainder.
• Conclusion: Pipelining or multi-cycle execution is recommended for the division operation in high-frequency target ASIC/FPGA implementations.

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📂 Repository Structure

├── Makefile                # Build system for Icarus Verilog simulation
├── README.md               # Architecture documentation & design report
├── program.asm             # Sample assembly program exercising ALU ops
├── program.hex             # Machine code hex file loaded into IMEM
├── rtl/                    # Verilog RTL Source Code
│   ├── alu.v               # Top-level ALU wrapper & operation mux
│   ├── control_unit.v      # Single-cycle opcode decoder & control signals
│   ├── decode.vh           # Instruction encoding macros and constants
│   ├── divider.v           # 32-bit combinational non-restoring divider
│   ├── encoder.v           # Radix-4 Booth partial product encoder
│   ├── fast_adders.v       # 32-bit & 64-bit Kogge-Stone parallel-prefix adders
│   ├── imem.v              # Instruction RAM/ROM & Data RAM modules
│   ├── immu.v              # Immediate extraction & sign-extension unit
│   ├── multiplier.v        # 32x32 Booth-Dadda-KSA multiplier
│   ├── regfile.v           # 16-entry x 32-bit Register File
│   ├── shifter.v           # 32-bit logarithmic barrel shifter
│   ├── simplerisc_top.v    # Top-level single-cycle SimpleRISC CPU core
│   ├── slt.v               # Signed Set-Less-Than comparator
│   └── tree_reducer.v      # 16-to-2 Dadda tree partial product reducer
├── tb/                     # Verification Testbenches
│   ├── tb_alu.v            # Unit testbench for stand-alone ALU core
│   └── tb_simplerisc.v     # System testbench for top-level SimpleRISC CPU
└── tools/
    └── asm.py              # Python assembly compiler (ASM -> HEX machine code)

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🛠️ Software Toolchain & Simulation Setup

1. Assembling Custom Programs

To assemble custom assembly instructions into machine code for execution:

python3 tools/asm.py program.asm program.hex

2. Simulating with Icarus Verilog

To compile and execute the top-level processor testbench:

make build
make run

To view simulation waveforms in GTKWave:

make wave