Use arm_embedded_module to simplify the runner in app_main

RTE/_Debug_SSE-320-U85/Pre_Include_Global.h

@@ -0,0 +1,25 @@
+/*
+ * CSOLUTION generated file: DO NOT EDIT!
+ * Generated by: csolution version 2.14.1+p38-gf512b381
+ *
+ * Project: 'cmsis-executorch-simple.Debug+SSE-320-U85' 
+ * Target:  'Debug+SSE-320-U85' 
+ */
+
+#ifndef PRE_INCLUDE_GLOBAL_H
+#define PRE_INCLUDE_GLOBAL_H
+
+/* ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U85@1.25.2 */
+// enabling global pre includes 
+        #define ETHOSU_ARCH u85
+/* PyTorch::Machine Learning:ExecuTorch:Backend EthosU@1.4.0 */
+#define EXECUTORCH_BUILD_ARM_BAREMETAL 1
+        #define ET_USE_ETHOS_U_BACKEND 1
+/* PyTorch::Machine Learning:ExecuTorch:Runtime@1.4.0 */
+/* ExecuTorch global configuration */
+        #define C10_USING_CUSTOM_GENERATED_MACROS
+        #define FLATBUFFERS_MAX_ALIGNMENT 1024
+        #define FLATBUFFERS_LOCALE_INDEPENDENT 0
+
+
+#endif /* PRE_INCLUDE_GLOBAL_H */

RTE/_Debug_SSE-320-U85/RTE_Components.h

@@ -0,0 +1,49 @@
+/*
+ * CSOLUTION generated file: DO NOT EDIT!
+ * Generated by: csolution version 2.14.1+p38-gf512b381
+ *
+ * Project: 'cmsis-executorch-simple.Debug+SSE-320-U85' 
+ * Target:  'Debug+SSE-320-U85' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+/*
+ * Define the Device Header File: 
+ */
+#define CMSIS_device_header "SSE320.h"
+
+/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */
+#define RTE_CMSIS_Compiler_STDERR                /* CMSIS-Compiler STDERR */
+#define RTE_CMSIS_Compiler_STDERR_Custom         /* CMSIS-Compiler STDERR: Custom */
+/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */
+#define RTE_CMSIS_Compiler_STDIN                 /* CMSIS-Compiler STDIN */
+#define RTE_CMSIS_Compiler_STDIN_Custom          /* CMSIS-Compiler STDIN: Custom */
+/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */
+#define RTE_CMSIS_Compiler_STDOUT                /* CMSIS-Compiler STDOUT */
+#define RTE_CMSIS_Compiler_STDOUT_Custom         /* CMSIS-Compiler STDOUT: Custom */
+/* ARM::Device:Native Driver:SysCounter@1.0.1 */
+#define RTE_SYSCOUNTER      1
+/* ARM::Device:Native Driver:Timeout@1.0.1 */
+#define RTE_TIMEOUT      1
+/* ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U85@1.25.2 */
+#define RTE_ETHOS_U_CORE_DRIVER
+/* PyTorch::Machine Learning:ExecuTorch Operators:Quantized dequantize@1.4.0 */
+#define RTE_ML_EXECUTORCH_OP_QUANTIZED_DEQUANTIZE     /* ExecuTorch op_dequantize */
+/* PyTorch::Machine Learning:ExecuTorch Operators:Quantized quantize@1.4.0 */
+#define RTE_ML_EXECUTORCH_OP_QUANTIZED_QUANTIZE     /* ExecuTorch op_quantize */
+/* PyTorch::Machine Learning:ExecuTorch:Backend EthosU@1.4.0 */
+#define RTE_ML_EXECUTORCH_BACKEND_ETHOS_U     /* ExecuTorch Ethos-U Backend (Cortex-M host) */
+/* PyTorch::Machine Learning:ExecuTorch:Extension Tensor@1.4.0 */
+#define RTE_ML_EXECUTORCH_EXTENSION_TENSOR     /* ExecuTorch Tensor Extension */
+/* PyTorch::Machine Learning:ExecuTorch:Kernel Registration@1.4.0 */
+#define RTE_ML_EXECUTORCH_KERNEL_REGISTRATION     /* ExecuTorch Kernel Registration */
+/* PyTorch::Machine Learning:ExecuTorch:Kernel Utils@1.4.0 */
+#define RTE_ML_EXECUTORCH_KERNEL_UTILS     /* ExecuTorch Kernel Utils */
+/* PyTorch::Machine Learning:ExecuTorch:Runtime@1.4.0 */
+#define RTE_ML_EXECUTORCH_RUNTIME     /* ExecuTorch Runtime */
+
+
+#endif /* RTE_COMPONENTS_H */

ai_layer/ai_layer.clayer.yml

@@ -15,6 +15,7 @@ layer:
     - component: Machine Learning:ExecuTorch:Runtime
     - component: Machine Learning:ExecuTorch:Kernel Utils
     - component: Machine Learning:ExecuTorch:Kernel Registration
+    - component: Machine Learning:ExecuTorch:Extension Tensor
     # Ethos-U NPU backend (the model is fully delegated to it).
     - component: Machine Learning:ExecuTorch:Backend EthosU
     # Quantized reference operators.

board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src

@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2023 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* ----------------------------------------------------------------------------
+  Stack seal size definition
+ *----------------------------------------------------------------------------*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define __STACKSEAL_SIZE 8
+#else
+#define __STACKSEAL_SIZE 0
+#endif
+
+/*----------------------------------------------------------------------------
+  Scatter File Definitions definition
+ *----------------------------------------------------------------------------*/
+
+LR_ROM0 __ROM0_BASE __ROM0_SIZE  {
+
+  ER_ROM0 __ROM0_BASE __ROM0_SIZE {
+    *.o (RESET, +First)
+    *(InRoot$$Sections)
+    *(+RO +XO)
+  }
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) {
+    *(Veneer$$CMSE)
+  }
+#endif
+
+  RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
+    *.o(.bss.noinit)
+    *.o(.bss.noinit.*)
+  }
+
+  RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
+    *(+RW +ZI)
+  }
+
+#if __HEAP_SIZE > 0
+  ARM_LIB_HEAP  (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE  {   ; Reserve empty region for heap
+  }
+#endif
+
+  ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
+  }
+
+#if __STACKSEAL_SIZE > 0
+  STACKSEAL +0 EMPTY __STACKSEAL_SIZE {             ; Reserve empty region for stack seal immediately after stack
+  }
+#endif
+
+#if __RAM1_SIZE > 0
+  RW_RAM1 __RAM1_BASE __RAM1_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM2_SIZE > 0
+  RW_RAM2 __RAM2_BASE __RAM2_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+
+#if __RAM3_SIZE > 0
+  RW_RAM3 __RAM3_BASE __RAM3_SIZE  {
+   .ANY (+RW +ZI)
+  }
+#endif
+}
+
+#if __ROM1_SIZE > 0
+LR_ROM1 __ROM1_BASE __ROM1_SIZE  {
+  ER_ROM1 +0 __ROM1_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM2_SIZE > 0
+LR_ROM2 __ROM2_BASE __ROM2_SIZE  {
+  ER_ROM2 +0 __ROM2_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif
+
+#if __ROM3_SIZE > 0
+LR_ROM3 __ROM3_BASE __ROM3_SIZE  {
+  ER_ROM3 +0 __ROM3_SIZE {
+   .ANY (+RO +XO)
+  }
+}
+#endif