board+plan: W0 is live on the 6502 — its main memory is not SpaceId::Ram - #1032
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The arch census over the real SLEIGH specs, run because W0 predicted the 6502 arc would fire first and that arc landed the same day: the 6502 declares five spaces and mints two custom ones. OTHER becomes Custom(0) on both architectures, and the 6502's own main memory RAM becomes Custom(1) because the alias map is seeded with lowercase names and resolved by exact HashMap hit. Every load and store on that architecture touches a space that is not SpaceId::Ram. Also corrects W0's own accounting in two places. Its census counted rows and found zero custom spaces; the arch always had one, since no row in those four binaries referenced OTHER. Both numbers are right and answer different questions. And W0 named two Custom sources where there are three: disasm.rs mints Custom from a wrapping byte-sum of the space name, so the chain loses identity to hash collisions before any ordering enters. The address consequence is stated conditionally on purpose. Whether a lifted 6502 varnode carries Custom(1) or Ram depends on which of two disagreeing translation paths produced it, and that half is read from source rather than observed. The unrun measurement that settles it is named. Verdict unchanged, urgency changed. The defect is upstream in r2sleigh, recorded here because it is the falsifier for a lance-graph verdict.
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August 25, 2026 21:14
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One commit. Docs/board only — no source change, no mint, no fix. W0's verdict is unchanged; what changes is that its "there is time" half is gone.
Why this ran
W0 (#1028) measured 0 custom spaces in 94,536 rows across four x86 binaries and predicted the case "fires first on the 6502/C64 arc." That arc landed the same day —
r2sleighPRs #2–#4 registered the 6502 family, wired the CLI, fetched the conformance corpus. The prediction was testable within hours, so it was tested.MEASURED — the arch census
build_arch_specover the real SLEIGH data, reporting theSpaceIdeach declared space maps to:constOTHERuniqueRAM→ CUSTOM(1)ram→ RamregisterThe 6502's main memory is not
SpaceId::Ram.context.rs:54-58seeds the alias map with lowercase names only andadd_space_with_endiannessresolves by exactHashMaphit; the 6502 spec spells its memoryRAM, misses, and falls through toCustom(1). Not a corner case — the space every load and store on that architecture touches.Two corrections to W0's own accounting, recorded not fixed silently
OTHERwas alwaysCustom(0). W0 counted rows, and no row in those four binaries referencedOTHER. Both numbers are correct and answer different questions; the entry says so rather than quietly replacing one with the other.Customsource, missed by W0:disasm.rs:770-775mintsCustom(hash)from a wrapping byte-sum of the space name. Every anagram collides. W0 said "two stages of order-dependence, zero of identity"; the real chain isname → byte-sum hash (colliding) → Custom(n) → sorted rank → classid lo-u16— three stages, and the first loses identity before any ordering enters.Stated conditionally on purpose
ordinal_of(1) = 5for the 6502, so if a varnode reachesfacet::projectcarryingCustom(1), its classid lo-u16 is 5 where x86's same concept is 0. The "if" is load-bearing:translate_space(disasm.rs:757-765) classifies byspace_type, not name, and would call that same spaceRam. Two paths, two answers for one space — and that half is read from source, not observed.The one measurement this entry does not have is named in it: lift a single 6502 memory access and read the
SpaceIdoff the varnode. That is the difference between "the 6502 addresses wrongly" and "the 6502 addresses correctly by accident, via the path that disagrees with its own ArchSpec."Scope
Not a lance-graph defect. The case-sensitive alias map and the divergent translation paths are
r2sleigh's, upstream of everything this plan owns. Recorded here because it is the falsifier for a lance-graph verdict — the fix is not proposed and does not belong in this repo.Test plan
r2sleigh-liftexample) was deleted after the run — both working trees verified clean.🤖 Generated with Claude Code
https://claude.ai/code/session_01AGVLyRZNEKKBSfBDJfbY3V
Generated by Claude Code