From 91a59a7fe59568ff4622a829483ebc78892c1636 Mon Sep 17 00:00:00 2001 From: Alex Lanzano Date: Sun, 30 Aug 2026 16:25:39 -0400 Subject: [PATCH] Add example for the NXP LPC55S6x platform --- nxp/lpc55s6x/.gitignore | 1 + nxp/lpc55s6x/Makefile | 163 +++++++++++++++++++++++++++++++++++ nxp/lpc55s6x/README.md | 147 +++++++++++++++++++++++++++++++ nxp/lpc55s6x/main.c | 142 ++++++++++++++++++++++++++++++ nxp/lpc55s6x/user_settings.h | 144 +++++++++++++++++++++++++++++++ 5 files changed, 597 insertions(+) create mode 100644 nxp/lpc55s6x/.gitignore create mode 100644 nxp/lpc55s6x/Makefile create mode 100644 nxp/lpc55s6x/README.md create mode 100644 nxp/lpc55s6x/main.c create mode 100644 nxp/lpc55s6x/user_settings.h diff --git a/nxp/lpc55s6x/.gitignore b/nxp/lpc55s6x/.gitignore new file mode 100644 index 000000000..567609b12 --- /dev/null +++ b/nxp/lpc55s6x/.gitignore @@ -0,0 +1 @@ +build/ diff --git a/nxp/lpc55s6x/Makefile b/nxp/lpc55s6x/Makefile new file mode 100644 index 000000000..1c8b4fd11 --- /dev/null +++ b/nxp/lpc55s6x/Makefile @@ -0,0 +1,163 @@ +# wolfCrypt test and benchmark for the NXP LPC55S6x (LPCXpresso55S69) +# +# MCUXSDK must point at an mcuxsdk-core checkout that west has populated, so +# that devices/, examples/ and components/ are present alongside drivers/: +# +# west init -m https://github.com/nxp-mcuxpresso/mcuxsdk-manifests mcuxsdk-ws +# cd mcuxsdk-ws && west update +# make MCUXSDK=/path/to/mcuxsdk-ws/mcuxsdk + +MCUXSDK ?= +WOLFSSL ?= ../../../wolfssl + +ifeq ($(MCUXSDK),) + ifneq ($(MAKECMDGOALS),clean) + $(error Set MCUXSDK to your mcuxsdk-core checkout, e.g. make MCUXSDK=~/mcuxsdk-ws/mcuxsdk) + endif +endif + +# Set to 0 to build the same algorithms in software, for comparison. +HW_CRYPTO ?= 1 + +CROSS_COMPILE ?= arm-none-eabi- +CC = $(CROSS_COMPILE)gcc +OBJCOPY = $(CROSS_COMPILE)objcopy +SIZE = $(CROSS_COMPILE)size + +BUILD = build +TARGET = wolfcrypt-lpc55s6x + +DEVICE = $(MCUXSDK)/devices/LPC/LPC5500/LPC55S69 +BOARDIR = $(MCUXSDK)/examples/_boards/lpcxpresso55s69 + +CPUFLAGS = -mcpu=cortex-m33 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 + +DEFINES = \ + -DCPU_LPC55S69JBD100_cm33_core0 \ + -DMCUXPRESSO_SDK \ + -DSDK_DEBUGCONSOLE=1 \ + -DPRINTF_FLOAT_ENABLE=1 \ + -DPRINTF_ADVANCED_ENABLE=1 \ + -DSERIAL_PORT_TYPE_UART=1 \ + -DWOLFSSL_USER_SETTINGS + +INCLUDES = \ + -I. \ + -I$(WOLFSSL) \ + -I$(MCUXSDK)/arch/arm/CMSIS/Core/Include \ + -I$(DEVICE) \ + -I$(MCUXSDK)/devices/LPC/LPC5500/periph \ + -I$(DEVICE)/drivers \ + -I$(MCUXSDK)/drivers/common \ + -I$(MCUXSDK)/drivers/flexcomm \ + -I$(MCUXSDK)/drivers/flexcomm/usart \ + -I$(MCUXSDK)/drivers/flexcomm/i2c \ + -I$(MCUXSDK)/drivers/lpc_gpio \ + -I$(MCUXSDK)/drivers/lpc_iocon \ + -I$(MCUXSDK)/drivers/casper \ + -I$(MCUXSDK)/drivers/hashcrypt \ + -I$(MCUXSDK)/drivers/rng_1 \ + -I$(MCUXSDK)/components/uart \ + -I$(MCUXSDK)/components/debug_console_lite \ + -I$(MCUXSDK)/components/str \ + -I$(BOARDIR) \ + -I$(BOARDIR)/project_template + +CFLAGS = $(CPUFLAGS) $(DEFINES) $(INCLUDES) \ + -Os -g3 -std=gnu99 -Wall \ + -ffunction-sections -fdata-sections -fno-common \ + -ffreestanding -fno-builtin -MMD -MP + +ASFLAGS = $(CPUFLAGS) -D__STARTUP_CLEAR_BSS -x assembler-with-cpp + +LDFLAGS = $(CPUFLAGS) \ + -T$(DEVICE)/gcc/LPC55S69_cm33_core0_flash.ld \ + --specs=nosys.specs --specs=nano.specs -u _printf_float \ + -Wl,--gc-sections -Wl,-Map=$(BUILD)/$(TARGET).map \ + -Wl,--defsym=__stack_size__=0x4000 \ + -Wl,--defsym=__heap_size__=0x8000 +LDLIBS = -lm -lc -lnosys + +# --- SDK ------------------------------------------------------------------- +SDK_SRCS = \ + $(DEVICE)/system_LPC55S69_cm33_core0.c \ + $(DEVICE)/drivers/fsl_clock.c \ + $(DEVICE)/drivers/fsl_power.c \ + $(DEVICE)/drivers/fsl_reset.c \ + $(MCUXSDK)/drivers/common/fsl_common.c \ + $(MCUXSDK)/drivers/common/fsl_common_arm.c \ + $(MCUXSDK)/drivers/flexcomm/fsl_flexcomm.c \ + $(MCUXSDK)/drivers/flexcomm/usart/fsl_usart.c \ + $(MCUXSDK)/drivers/rng_1/fsl_rng.c \ + $(MCUXSDK)/components/uart/fsl_adapter_usart.c \ + $(MCUXSDK)/components/debug_console_lite/fsl_debug_console.c \ + $(MCUXSDK)/components/str/fsl_str.c \ + $(BOARDIR)/board.c \ + $(BOARDIR)/clock_config.c \ + $(BOARDIR)/project_template/pin_mux.c + +ASM_SRCS = $(DEVICE)/gcc/startup_LPC55S69_cm33_core0.S + +# --- wolfSSL --------------------------------------------------------------- +WOLF_SRCS = \ + $(WOLFSSL)/wolfcrypt/src/wc_port.c \ + $(WOLFSSL)/wolfcrypt/src/memory.c \ + $(WOLFSSL)/wolfcrypt/src/logging.c \ + $(WOLFSSL)/wolfcrypt/src/error.c \ + $(WOLFSSL)/wolfcrypt/src/wolfmath.c \ + $(WOLFSSL)/wolfcrypt/src/hash.c \ + $(WOLFSSL)/wolfcrypt/src/hmac.c \ + $(WOLFSSL)/wolfcrypt/src/sha.c \ + $(WOLFSSL)/wolfcrypt/src/sha256.c \ + $(WOLFSSL)/wolfcrypt/src/aes.c \ + $(WOLFSSL)/wolfcrypt/src/wc_encrypt.c \ + $(WOLFSSL)/wolfcrypt/src/rsa.c \ + $(WOLFSSL)/wolfcrypt/src/asn.c \ + $(WOLFSSL)/wolfcrypt/src/coding.c \ + $(WOLFSSL)/wolfcrypt/src/kdf.c \ + $(WOLFSSL)/wolfcrypt/src/random.c \ + $(WOLFSSL)/wolfcrypt/src/sp_int.c \ + $(WOLFSSL)/wolfcrypt/src/sp_cortexm.c + +APP_SRCS = main.c \ + $(WOLFSSL)/wolfcrypt/test/test.c \ + $(WOLFSSL)/wolfcrypt/benchmark/benchmark.c + +ifeq ($(HW_CRYPTO),0) +DEFINES += -DWOLFSSL_LPC55S6X_SOFTWARE_ONLY +else +SDK_SRCS += \ + $(MCUXSDK)/drivers/casper/fsl_casper.c \ + $(MCUXSDK)/drivers/hashcrypt/fsl_hashcrypt.c +WOLF_SRCS += \ + $(WOLFSSL)/wolfcrypt/src/port/nxp/casper_port.c \ + $(WOLFSSL)/wolfcrypt/src/port/nxp/hashcrypt_port.c +endif + +SRCS = $(SDK_SRCS) $(WOLF_SRCS) $(APP_SRCS) +OBJS = $(addprefix $(BUILD)/,$(notdir $(SRCS:.c=.o)) $(notdir $(ASM_SRCS:.S=.o))) +VPATH = $(sort $(dir $(SRCS) $(ASM_SRCS))) + +.PHONY: all clean +all: $(BUILD)/$(TARGET).bin + +$(BUILD)/$(TARGET).bin: $(BUILD)/$(TARGET).elf + $(OBJCOPY) -O binary $< $@ + +$(BUILD)/$(TARGET).elf: $(OBJS) + $(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS) + @$(SIZE) $@ + +$(BUILD)/%.o: %.c | $(BUILD) + $(CC) $(CFLAGS) -c -o $@ $< + +$(BUILD)/%.o: %.S | $(BUILD) + $(CC) $(ASFLAGS) -c -o $@ $< + +$(BUILD): + mkdir -p $@ + +clean: + rm -rf $(BUILD) + +-include $(OBJS:.o=.d) diff --git a/nxp/lpc55s6x/README.md b/nxp/lpc55s6x/README.md new file mode 100644 index 000000000..fb7e00263 --- /dev/null +++ b/nxp/lpc55s6x/README.md @@ -0,0 +1,147 @@ +# wolfCrypt test and benchmark for the NXP LPC55S6x + +A single application for the LPCXpresso55S69 that runs `wolfcrypt_test()` and +then `benchmark_test()` over the debug UART, configured for exactly the +algorithms the wolfSSL NXP LPC55S6x port accelerates in hardware. + +## What is accelerated + +`WOLFSSL_NXP_LPC55S6X` enables three blocks: + +| Block | Covers | +| --------- | --------------------------------------------------- | +| RNG | TRNG, used to seed the Hash-DRBG | +| HashCrypt | AES-128/192/256 ECB, CBC, CTR; SHA-1, SHA-256 | +| CASPER | RSA public key operations (ECC: see below) | + +`user_settings.h` enables those and nothing else, so both the test and the +benchmark report only what this part actually accelerates. Everything the +LPC55S6x has no engine for -- Curve25519, ChaCha20-Poly1305, AES-GCM/CCM, +SHA-512, SHA-3, MD5, 3DES -- is left out. + +RSA is the one split case. CASPER handles only the *public* half; the hook for +it in `wc_RsaFunctionSync()` (`rsa.c`) sits ahead of the SP path, so SP math +with Cortex-M assembly picks up the private key operations. + +### ECC is absent because the port cannot reach CASPER's ECC + +CASPER does accelerate ECC, and `casper_port.c` implements it -- `casper_ecc_mulmod()` +and `casper_ecc_mul2add()`, with P-256, P-384 and P-521 branches, driving the +SDK's `CASPER_ECC_SECP256R1_Mul()` and friends. Nothing calls them. `ecc.c` has +no reference to CASPER at all, and `WOLFSSL_NXP_CASPER_ECC_MULMOD` and +`WOLFSSL_NXP_CASPER_ECC_MUL2ADD` appear nowhere outside `casper_port.c` itself. + +The history explains it: commit `3878271e3` added those functions and, in the +same change, commented out `WOLFSSL_NXP_CASPER_ECC_MUL2ADD` and +`WOLFSSL_SP_MULMOD` in `settings.h`. `WOLFSSL_SP_MULMOD` -- the SP-math hook +the accelerated path was meant to arrive through -- does not exist anywhere in +wolfSSL. `WOLFSSL_NXP_LPC55S6X` consequently defines only +`WOLFSSL_NXP_CASPER_RSA_PUB_EXPTMOD`. + +So `HAVE_ECC` here would give software ECC, not accelerated ECC, which is not +what this example is for. Enable it if you want a software baseline; the +hardware numbers will not change until the ecc.c side is wired up. + +### CFB and OFB are deliberately absent + +HashCrypt also accelerates AES-CFB and AES-OFB, and `hashcrypt_port.c` +implements both, but only for whole 16-byte blocks. `wolfcrypt_test()` drives +them with sub-block lengths on purpose -- 8-byte calls in `aesofb_test()`, 4 +and 27 bytes in `aescfb_test()` -- so enabling them would report failures that +say nothing about the hardware. Define `WOLFSSL_AES_CFB` and `WOLFSSL_AES_OFB` +in `user_settings.h` if you want them in the benchmark and can accept that. + +The same caveat list also notes that AES-CTR fails when the counter wraps from +all-`FF` to zero. The test suite's counter-wrap vectors are already compiled +out for this configuration. + +### WOLFSSL_CRYPT_HW_MUTEX is pinned off + +`wc_port.h` turns `WOLFSSL_CRYPT_HW_MUTEX` on whenever `WOLFSSL_NXP_CASPER` is +defined, and `hashcrypt_port.c` has an `#error` against exactly that -- so the +two halves of `WOLFSSL_NXP_LPC55S6X` will not compile together at the default +setting. `user_settings.h` pins it to 0. This build is `SINGLE_THREADED`, where +the mutex compiles away to a stub, so nothing is lost; a threaded build on this +part would need the port fixed first. + +## Building + +The port is built against the NXP MCUXpresso SDK, which the Makefile locates +through `MCUXSDK`. Point it at an `mcuxsdk-core` checkout that west has +populated, so `devices/`, `examples/` and `components/` sit alongside +`drivers/`: + +```sh +west init -m https://github.com/nxp-mcuxpresso/mcuxsdk-manifests mcuxsdk-ws +cd mcuxsdk-ws && west update +``` + +wolfSSL is expected as a sibling of `wolfssl-examples`; override `WOLFSSL` if +it is elsewhere. Then, in this directory: + +```sh +make MCUXSDK=/path/to/mcuxsdk-ws/mcuxsdk +``` + +That produces `build/wolfcrypt-lpc55s6x.elf` and `.bin`. A recent +`arm-none-eabi-gcc` is needed; set `CROSS_COMPILE` if yours is prefixed +differently. + +To measure what the hardware is worth, build the identical algorithm set in +software: + +```sh +make clean && make MCUXSDK=/path/to/mcuxsdk-ws/mcuxsdk HW_CRYPTO=0 +``` + +The TRNG stays on in both, since it is the board's only entropy source -- the +two builds differ only in the AES, SHA and RSA implementations. + +## Running + +Flash the `.bin` to the LPCXpresso55S69 and open the board's debug UART at +**115200 8N1**. It comes up on FLEXCOMM0 (`PIO0_29`/`PIO0_30`), which is the +LPC-Link2 virtual COM port. + +The application boots at 150 MHz, initialises the TRNG, runs the test suite, +then the benchmark, and halts. + +## Notes on the code + +`main.c` does three things worth pointing out: + +- It calls `RNG_Init(RNG)` before `wolfCrypt_Init()`. wolfSSL's + `wc_GenerateSeed()` calls `RNG_GetRandomData()` directly and never + initialises the peripheral, so the ring oscillator has to be powered and the + entropy accumulator warmed up by the application. +- `current_time()` backs the benchmark's timebase with SysTick. It reads the + reload counter alongside the millisecond count, because at 150 MHz HashCrypt + routinely finishes an operation inside a single 1 ms tick. +- `wolfCrypt_Init()` is what brings up CASPER and HashCrypt, via + `wc_casper_init()` and `wc_hashcrypt_init()`. There is no separate hardware + init to call. +- `wolf_printf()` is what `XPRINTF` points at, so that `printf` inside + `test.c` and `benchmark.c` routes through it. wolfCrypt ends its lines with + a bare `\n` and neither SDK debug console translates that, which staircases + the output on a serial terminal. Rather than buffer whole lines, it formats + with the SDK's `StrFormatPrintf()` and inserts the CR in the character + callback. That also means the lite console's own formatter goes unreferenced + and the linker drops it, so the image is slightly smaller than it was with + `XPRINTF` mapped straight to `PRINTF`. + +Board support -- `board.c`, `clock_config.c`, `pin_mux.c` -- is compiled +straight out of the SDK tree rather than copied here, so there is nothing to +re-sync when the SDK moves. + +## Status + +Both configurations build clean and the hardware paths are the ones that link: +`wc_Sha256Update`, `wc_ShaUpdate`, `wc_AesCbcEncrypt` and `wc_AesCtrEncrypt` +all resolve to `hashcrypt_port.o`, and `casper_rsa_public_exptmod` to +`casper_port.o`. + +The newline handling was checked by compiling `fsl_str.c` and the callback for +the host and running wolfCrypt-shaped format strings through them: every `\n` +came out as `\r\n`, with float, width and hex conversions intact. + +The images have not been run on hardware. diff --git a/nxp/lpc55s6x/main.c b/nxp/lpc55s6x/main.c new file mode 100644 index 000000000..14038e95e --- /dev/null +++ b/nxp/lpc55s6x/main.c @@ -0,0 +1,142 @@ +/* main.c + * + * wolfCrypt test and benchmark for the NXP LPC55S6x. + * + * Copyright (C) 2006-2026 wolfSSL Inc. + * + * This file is part of wolfSSL. + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#include "user_settings.h" + +#include + +#include "fsl_device_registers.h" +#include "fsl_debug_console.h" +#include "fsl_str.h" +#include "fsl_rng.h" +#include "board.h" +#include "pin_mux.h" +#include "clock_config.h" + +#include +#include +#include +#include + +static volatile uint32_t g_tickMs; + +/* wolfCrypt's test and benchmark end their lines with a bare \n, which + * staircases on a serial terminal. StrFormatPrintf() formats straight into a + * character callback, so the CR goes in here: no line buffer to size, and no + * second printf implementation linked in beside the console's own. */ +static void lpc_put_cb(char* buf, int32_t* count, char val, int len) +{ + int i; + + (void)buf; + + for (i = 0; i < len; i++) { + if (val == '\n') + (void)DbgConsole_Putchar('\r'); + (void)DbgConsole_Putchar(val); + (*count)++; + } +} + +/* XPRINTF in user_settings.h points wolfCrypt's printf here. */ +int wolf_printf(const char* fmt, ...) +{ + va_list ap; + char unused; + int ret; + + va_start(ap, fmt); + ret = StrFormatPrintf(fmt, ap, &unused, lpc_put_cb); + va_end(ap); + + return ret; +} + +void SysTick_Handler(void) +{ + g_tickMs++; +} + +/* WOLFSSL_USER_CURRTIME routes the benchmark's timebase here. SysTick's + * reload counter is read alongside the millisecond count so that operations + * finishing inside a single tick -- which HashCrypt regularly does at 150 MHz + * -- still land on a meaningful number. */ +double current_time(int reset) +{ + uint32_t ms, val, load; + + (void)reset; + + do { + ms = g_tickMs; + val = SysTick->VAL; + } while (ms != g_tickMs); + + load = SysTick->LOAD + 1U; + + return (double)ms / 1000.0 + + (double)(load - val) / ((double)load * 1000.0); +} + +int main(void) +{ + int ret; + + BOARD_InitBootPins(); + BOARD_BootClockPLL150M(); + BOARD_InitDebugConsole(); + + SysTick_Config(SystemCoreClock / 1000U); + + /* wc_GenerateSeed() calls RNG_GetRandomData() directly and does not + * initialize the peripheral, so the ring oscillator has to be powered and + * the entropy accumulator warmed up here. */ + RNG_Init(RNG); + + wolf_printf("\nwolfCrypt on LPC55S6x @ %u MHz\n", + (unsigned)(SystemCoreClock / 1000000U)); +#ifdef WOLFSSL_NXP_LPC55S6X + wolf_printf("Hardware acceleration: TRNG, HashCrypt (AES/SHA), CASPER (RSA)\n"); +#else + wolf_printf("Hardware acceleration: disabled (software only)\n"); +#endif + + ret = wolfCrypt_Init(); + if (ret != 0) { + wolf_printf("wolfCrypt_Init failed: %d\n", ret); + while (1) { } + } + + wolf_printf("\n--- wolfCrypt test ---\n"); + ret = wolfcrypt_test(NULL); + wolf_printf("wolfcrypt_test returned %d\n", ret); + + wolf_printf("\n--- wolfCrypt benchmark ---\n"); + ret = benchmark_test(NULL); + wolf_printf("benchmark_test returned %d\n", ret); + + wolfCrypt_Cleanup(); + + wolf_printf("\nDone.\n"); + while (1) { } +} diff --git a/nxp/lpc55s6x/user_settings.h b/nxp/lpc55s6x/user_settings.h new file mode 100644 index 000000000..2493877d3 --- /dev/null +++ b/nxp/lpc55s6x/user_settings.h @@ -0,0 +1,144 @@ +/* user_settings.h + * + * Copyright (C) 2006-2026 wolfSSL Inc. + * + * This file is part of wolfSSL. + * + * wolfSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * wolfSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WOLFSSL_USER_SETTINGS_LPC55S6X_H +#define WOLFSSL_USER_SETTINGS_LPC55S6X_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "fsl_debug_console.h" + +/* Hardware acceleration. WOLFSSL_NXP_LPC55S6X pulls in the whole LPC55S6x + * port: the TRNG, HashCrypt (AES and SHA) and CASPER (RSA public key). The + * Makefile leaves it out for HW_CRYPTO=0, which builds the same algorithm set + * in software to compare against. */ +#ifndef WOLFSSL_LPC55S6X_SOFTWARE_ONLY + #define WOLFSSL_NXP_LPC55S6X +#endif + +/* The TRNG stays on in both builds -- it is the board's only entropy source, + * and keeping it fixed means the HW_CRYPTO=0 comparison differs only in the + * AES/SHA/RSA implementations. */ +#define WOLFSSL_NXP_RNG_1 + +/* WOLFSSL_NXP_CASPER makes wc_port.h turn WOLFSSL_CRYPT_HW_MUTEX on, but + * hashcrypt_port.c has an #error against exactly that, so the two halves of + * WOLFSSL_NXP_LPC55S6X will not compile together at the default setting. + * SINGLE_THREADED means the mutex is a no-op anyway, so pin it off here -- + * wolfSSL_HwPkMutexInit() then resolves to the stub in wc_port.h. */ +#define WOLFSSL_CRYPT_HW_MUTEX 0 + +/* Platform */ +#define WOLFSSL_GENERAL_ALIGNMENT 4 +#define SINGLE_THREADED +#define WOLFCRYPT_ONLY +#define SIZEOF_LONG_LONG 8 +#define NO_FILESYSTEM +#define NO_WOLFSSL_DIR +#define WOLFSSL_NO_CURRDIR +#define NO_WRITEV +#define NO_DEV_RANDOM +#define NO_MAIN_DRIVER +#define WOLFSSL_NO_SOCK +#define WOLFSSL_IGNORE_FILE_WARN +#define WOLFSSL_SMALL_STACK + +/* No RTC on the board, so certificate validity dates cannot be checked. */ +#define NO_ASN_TIME + +/* Output and the benchmark timebase both come from the board: PRINTF is the + * SDK debug console, current_time() is the SysTick counter in main.c. */ +#define BENCH_EMBEDDED +#define WOLFSSL_USER_CURRTIME + +/* Not PRINTF directly: the test and benchmark terminate lines with a bare \n, + * and neither SDK debug console translates it. wolf_printf() in main.c adds + * the CR as it formats. */ +int wolf_printf(const char* fmt, ...); +#define XPRINTF wolf_printf + +/* Math. CASPER only accelerates RSA *public* operations, and its hook in + * wc_RsaFunctionSync() runs ahead of the SP path, so SP is what ends up doing + * the private key half -- worth having the Cortex-M assembly for. */ +#define WOLFSSL_SP_MATH_ALL +#define WOLFSSL_HAVE_SP_RSA +#define WOLFSSL_SP_ASM +#define WOLFSSL_SP_ARM_CORTEX_M_ASM +#define SP_WORD_SIZE 32 + +/* + * Enabled algorithms. These are exactly what the LPC55S6x port accelerates: + * + * HashCrypt AES-128/192/256 ECB, CBC and CTR + * SHA-1, SHA-256 + * CASPER RSA public key operations. CASPER accelerates ECC too and + * casper_port.c implements casper_ecc_mulmod()/mul2add(), but + * nothing in ecc.c calls them, so ECC would be software-only + * here -- see README.md. + * RNG TRNG, used to seed the Hash-DRBG + * + * HashCrypt also covers CFB and OFB, but only for whole 16-byte blocks, and + * wolfcrypt_test() drives both with sub-block lengths (8 bytes in + * aesofb_test, 4 and 27 in aescfb_test). They are left out so the test suite + * runs clean; see README.md. + */ +#define HAVE_AES_ECB +#define WOLFSSL_AES_COUNTER +#define WOLFSSL_AES_DIRECT +#define WOLFSSL_AES_128 +#define WOLFSSL_AES_192 +#define WOLFSSL_AES_256 + +#define HAVE_RSA +#define WC_RSA_BLINDING +#define RSA_LOW_MEM +#define USE_CERT_BUFFERS_2048 + +/* HMAC and the Hash-DRBG both sit on top of the accelerated SHA cores. */ +#define HAVE_HASHDRBG + +/* Disabled: nothing reaches hardware for any of these on this part. */ +#define NO_MD4 +#define NO_MD5 +#define NO_RC4 +#define NO_DES3 +#define NO_DSA +#define NO_DH +#define NO_PWDBASED +#define NO_PKCS12 +#define NO_PKCS7 +#define NO_SIG_WRAPPER +#define NO_SESSION_CACHE +#define NO_OLD_TLS +#define NO_OLD_RNGNAME +#define WOLFSSL_NO_PEM + +/* Hashes HashCrypt has no engine for */ +#define WOLFSSL_NO_SHA224 +#define NO_SHA512 + +#ifdef __cplusplus +} +#endif + +#endif /* WOLFSSL_USER_SETTINGS_LPC55S6X_H */