diff --git a/.github/workflows/build-lancedb.yml b/.github/workflows/build-lancedb.yml
new file mode 100644
index 000000000..b845c502f
--- /dev/null
+++ b/.github/workflows/build-lancedb.yml
@@ -0,0 +1,195 @@
+# SPDX-FileCopyrightText: 2026 The RISE Project
+# SPDX-License-Identifier: MIT
+---
+# This workflow is based on the `linux` job of
+# https://github.com/lancedb/lancedb/blob/v0.37.1/.github/workflows/pypi-publish.yml
+name: Build lancedb wheels (riscv64)
+
+on:
+  workflow_dispatch:
+    inputs:
+      version:
+        description: 'lancedb version to build (git tag without the leading v, e.g. 0.37.1)'
+        required: true
+        default: '0.37.1'
+  pull_request:
+    paths:
+      - '.github/workflows/build-lancedb.yml'
+
+concurrency:
+  group: ${{ github.workflow }}-${{ inputs.version || '0.37.1' }}-${{ github.head_ref || github.run_id }}
+  cancel-in-progress: true
+
+permissions:
+  contents: read  # to fetch code (actions/checkout)
+
+env:
+  # `inputs.version` is empty on pull_request events; default to 0.37.1 there.
+  LANCEDB_VERSION: ${{ inputs.version || '0.37.1' }}
+  MANYLINUX_RISCV64_IMAGE: quay.io/pypa/manylinux_2_39_riscv64
+  CARGO_INCREMENTAL: 0
+  CARGO_NET_RETRY: 10
+  RUSTUP_MAX_RETRIES: 10
+
+jobs:
+  setup:
+    uses: $/.github/workflows/_setup.yml
+
+  build_wheels:
+    needs: [setup]
+    name: Build lancedb ${{ inputs.version || '0.37.1' }} cp310-abi3-manylinux_riscv64
+    runs-on: ubuntu-24.04-riscv
+    timeout-minutes: 1440
+
+    steps:
+      # lancedb-python is a member of the lancedb Cargo workspace and builds
+      # against its sibling crates, so the checkout lands at the workspace root.
+      - name: Checkout lancedb v${{ env.LANCEDB_VERSION }}
+        uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1  # v7.0.1
+        with:
+          repository: lancedb/lancedb
+          ref: v${{ env.LANCEDB_VERSION }}
+          persist-credentials: false
+
+      - name: Checkout python-wheels
+        uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1  # v7.0.1
+        with:
+          path: python-wheels
+          sparse-checkout: patches/lancedb
+          persist-credentials: false
+
+      - name: Apply lancedb patches
+        run: git apply -v python-wheels/patches/lancedb/${{ env.LANCEDB_VERSION }}/0001*.patch
+
+      # lance-core's SIMD_SUPPORT static and lance-linalg's f32x8/f32x16/
+      # i32x8/f64x4/f64x8 SIMD types compile only for x86_64/aarch64/
+      # loongarch64 upstream; the 0002 patch adds a portable riscv64 fallback
+      # to this checkout, and Cargo.toml's `[patch.crates-io]` (0001) redirects
+      # both crates here.
+      - name: Checkout lance v10.0.0 and add a riscv64 SIMD fallback
+        uses: actions/checkout@3d3c42e5aac5ba805825da76410c181273ba90b1  # v7.0.1
+        with:
+          repository: lancedb/lance
+          ref: v10.0.0
+          path: lance
+          persist-credentials: false
+
+      - name: Apply lance patches
+        run: cd lance && git apply -v ../python-wheels/patches/lancedb/${{ env.LANCEDB_VERSION }}/0002*.patch
+
+      - name: Free disk space
+        uses: jlumbroso/free-disk-space@54081f138730dfa15788a46383842cd2f914a1be  # v1.3.1
+
+      # Same OOM guard build-deltalake.yml/build-polars-runtime.yml need on
+      # these runners for a comparably sized Rust workspace.
+      - name: Set swap space
+        uses: pierotofy/set-swap-space@fc79b3f67fa8a838184ce84a674ca12238d2c761  # master
+        with:
+          swap-size-gb: 16
+
+      - name: Build wheel
+        uses: pypa/cibuildwheel@1828c10ab37f080699c7b81cea34097c684a7074  # v4.2.0
+        with:
+          package-dir: python
+          output-dir: wheelhouse/
+          # pyo3 carries `abi3-py310` unconditionally in python/Cargo.toml, so
+          # upstream ships one cp310-abi3 wheel and no free-threaded variant:
+          # one build, on our minimum interpreter (build-deltalake.yml is the
+          # same shape). musllinux is dropped: rustup.rs ships no riscv64 musl
+          # toolchain. The x86_64-only `lancedb-compat` package variant
+          # (pre-Haswell CPU baseline) and the `fp16kernels` feature
+          # (lance-linalg's build.rs hard-errors compiling its C kernels for
+          # any target_arch other than x86_64/aarch64/loongarch64) have no
+          # riscv64 equivalent, so neither is built here.
+          only: cp312-manylinux_riscv64
+        env:
+          CIBW_MANYLINUX_RISCV64_IMAGE: ${{ env.MANYLINUX_RISCV64_IMAGE }}
+          # lancedb ships no [tool.cibuildwheel], so the Rust toolchain its
+          # maturin backend needs is installed in-container here. Rocky 10's
+          # CRB repo (enabled in the manylinux image) has protoc; PROTOC_INCLUDE
+          # is needed because it resolves google/protobuf/*.proto from disk
+          # rather than from the binary (same as build-statsig-python-core.yml).
+          CIBW_BEFORE_ALL_LINUX: >-
+            yum install -y protobuf-compiler protobuf-devel &&
+            curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y --profile minimal
+          # .cargo/config.toml's [profile.release] is fat LTO + codegen-units=1,
+          # which this runner cannot afford for a workspace this size (arrow,
+          # datafusion, the aws/gcp/azure/tencent/huggingface object-store
+          # backends, lance-index). Upstream's own `release-with-debug` profile
+          # exists for exactly this tradeoff (thin LTO, codegen-units=16), so
+          # the override matches a shape upstream already ships rather than
+          # inventing one (same reasoning as build-deltalake.yml).
+          CIBW_ENVIRONMENT_LINUX: >-
+            PATH="$PATH:$HOME/.cargo/bin"
+            PROTOC=/usr/bin/protoc
+            PROTOC_INCLUDE=/usr/include
+            CARGO_PROFILE_RELEASE_LTO=thin
+            CARGO_PROFILE_RELEASE_CODEGEN_UNITS=16
+            CARGO_BUILD_JOBS=2
+            PIP_EXTRA_INDEX_URL=https://pypi.riseproject.dev/simple/
+          # Without this pip prefers PyPI's releases, which have no riscv64
+          # wheel for these, and source-builds them in the container.
+          CIBW_TEST_ENVIRONMENT: PIP_ONLY_BINARY=numpy,pandas,pyarrow,duckdb,pydantic-core
+          CIBW_TEST_REQUIRES: pytest pytest-asyncio numpy pandas pyarrow duckdb
+          CIBW_TEST_SOURCES: python/pyproject.toml python/python/tests
+          # test_table.py, test_util.py, test_embeddings.py and
+          # test_namespace_integration.py import `polars` and/or `lance`
+          # (pylance) unconditionally at module scope, as do
+          # docs/test_guide_tables.py and docs/test_python.py; neither package
+          # has a riscv64 wheel and both are large enough Rust projects in
+          # their own right that building them from source here is out of
+          # scope, so those six files fail collection and are excluded rather
+          # than left to error. Otherwise mirrors run_tests/action.yml's
+          # non-integration path (`-m "not slow and not s3_test"`, no docker
+          # compose/localstack).
+          #
+          # The 13 deselects below are individual tests (not whole files, since
+          # each file has other tests that do pass) confirmed failing in CI run
+          # 33791589510: 12 import `lance`/`polars` lazily inside the test body
+          # rather than at module scope, so they collect fine but fail at
+          # runtime with the same "no riscv64 wheel" cause as the six ignored
+          # files above. The 13th, test_pyo3_abi_matches_minimum_supported_python,
+          # is a source-tree sanity check that reads python/Cargo.toml relative
+          # to the test file's own path; CIBW_TEST_SOURCES only copies
+          # pyproject.toml and python/tests into the isolated test dir (no
+          # Cargo.toml), so it fails with FileNotFoundError regardless of
+          # platform -- it checks repo metadata consistency, not runtime
+          # behavior, so it has nothing to verify against an installed wheel.
+          CIBW_TEST_COMMAND: >-
+            python -m pytest python/python/tests -vv --durations=30
+            -m "not slow and not s3_test"
+            --ignore=python/python/tests/test_table.py
+            --ignore=python/python/tests/test_util.py
+            --ignore=python/python/tests/test_embeddings.py
+            --ignore=python/python/tests/test_namespace_integration.py
+            --ignore=python/python/tests/docs/test_guide_tables.py
+            --ignore=python/python/tests/docs/test_python.py
+            --deselect=python/python/tests/test_db.py::test_create_table_stable_row_ids_via_storage_options
+            --deselect=python/python/tests/test_db.py::test_create_table_stable_row_ids_via_storage_options_sync
+            --deselect=python/python/tests/test_db.py::test_create_table_stable_row_ids_table_level_override
+            --deselect=python/python/tests/test_db.py::test_create_table_stable_row_ids_table_level_override_sync
+            --deselect=python/python/tests/test_db.py::test_namespace_client_native_storage
+            --deselect=python/python/tests/test_db.py::test_namespace_client_with_storage_options
+            --deselect=python/python/tests/test_db.py::test_namespace_client_operations
+            --deselect=python/python/tests/test_db.py::test_namespace_client_namespace_connection
+            --deselect=python/python/tests/test_hybrid_query.py::test_hybrid_query_with_stale_fixed_size_binary_prefilter
+            --deselect=python/python/tests/test_package_metadata.py::test_pyo3_abi_matches_minimum_supported_python
+            --deselect=python/python/tests/test_permutation.py::test_transform_fn
+            --deselect=python/python/tests/test_query.py::test_query_to_polars_async
+            --deselect=python/python/tests/test_query.py::test_blob_v2_with_row_id_bytes_pandas
+
+      - uses: actions/upload-artifact@043fb46d1a93c77aae656e7c1c64a875d1fc6a0a  # v7.0.1
+        with:
+          name: lancedb-${{ env.LANCEDB_VERSION }}-cp310-abi3-manylinux_riscv64
+          path: wheelhouse/*.whl
+          if-no-files-found: error
+
+  publish:
+    name: Publish lancedb ${{ inputs.version || '0.37.1' }}
+    needs: [setup, build_wheels]
+    permissions:
+      contents: write
+      pull-requests: write
+    uses: $/.github/workflows/_publish-wheel.yml
+    with:
+      artifact-pattern: lancedb-${{ inputs.version || '0.37.1' }}-*-manylinux_riscv64
diff --git a/patches/lancedb/0.37.1/0001-cargo-redirect-lance-core-lance-linalg-to-a-riscv64.patch b/patches/lancedb/0.37.1/0001-cargo-redirect-lance-core-lance-linalg-to-a-riscv64.patch
new file mode 100644
index 000000000..4be13c597
--- /dev/null
+++ b/patches/lancedb/0.37.1/0001-cargo-redirect-lance-core-lance-linalg-to-a-riscv64.patch
@@ -0,0 +1,64 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Ludovic Henry <git@ludovic.dev>
+Date: Thu, 03 Sep 2026 00:00:00 +0000
+Subject: [PATCH] cargo: redirect lance-core/lance-linalg to a riscv64-patched
+ checkout
+
+lance-core's SIMD_SUPPORT static (rust/lance-core/src/utils/cpu.rs) and
+lance-linalg's f32x8/f32x16/i32x8/f64x4/f64x8 SIMD types
+(rust/lance-linalg/src/simd/{f32,i32,f64}.rs) are compiled for
+x86_64/aarch64/loongarch64 only, with no fallback arm for any other
+architecture: the SIMD_SUPPORT closure has no trailing expression on
+riscv64 ("expected SimdSupport, found ()"), and the SIMD type structs are
+defined only under those three `#[cfg(target_arch = ...)]` attributes
+while every method implementing them is unconditional, so riscv64 hits
+"cannot find type `f32x8` in this scope" as soon as lance-linalg is
+built.
+
+Both crates are pulled in from crates.io at a pinned `=10.0.0`, so the
+fix cannot be applied in place. Redirect them to a checkout of the same
+v10.0.0 tag carrying a portable scalar fallback for both, see
+0002-lance-linalg-add-a-portable-riscv64-simd-fallback.patch. `exclude`
+keeps that checkout's own [workspace] from being silently absorbed into
+this one, which would drop its `[workspace.package]` inheritance
+(version, edition, ...) for lance-core and lance-linalg.
+
+Only the source line of the lance-core/lance-linalg entries changes in
+Cargo.lock, so every other dependency stays pinned exactly as upstream
+released it.
+
+Upstream-Status: Inappropriate [redirects two pinned dependencies to a local checkout; the fix itself belongs in lancedb/lance]
+
+Signed-off-by: Ludovic Henry <git@ludovic.dev>
+---
+ Cargo.toml | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/Cargo.toml b/Cargo.toml
+index a47e59e..ab6cf5c 100644
+--- a/Cargo.toml
++++ b/Cargo.toml
+@@ -1,5 +1,10 @@
+ [workspace]
+ members = ["rust/lancedb", "nodejs", "python"]
++# ./lance (see [patch.crates-io] below) carries its own [workspace]; excluding
++# it keeps that workspace independent instead of being silently absorbed into
++# this one, which would drop its `[workspace.package]` inheritance (version,
++# edition, ...) for lance-core and lance-linalg.
++exclude = ["lance"]
+ resolver = "2"
+ 
+ [workspace.package]
+@@ -80,3 +85,10 @@ debug = false
+ debug-assertions = false
+ strip = "debuginfo"
+ incremental = false
++
++# lance-core's SIMD_SUPPORT and lance-linalg's f32x8/f32x16/i32x8/f64x4/f64x8
++# SIMD types compile only for x86_64/aarch64/loongarch64 upstream; ./lance is
++# the same v10.0.0 tag with a riscv64 scalar fallback added to both.
++[patch.crates-io]
++lance-core = { path = "lance/rust/lance-core" }
++lance-linalg = { path = "lance/rust/lance-linalg" }
+-- 
+2.43.0
diff --git a/patches/lancedb/0.37.1/0002-lance-linalg-add-a-portable-riscv64-simd-fallback.patch b/patches/lancedb/0.37.1/0002-lance-linalg-add-a-portable-riscv64-simd-fallback.patch
new file mode 100644
index 000000000..dca48b993
--- /dev/null
+++ b/patches/lancedb/0.37.1/0002-lance-linalg-add-a-portable-riscv64-simd-fallback.patch
@@ -0,0 +1,1288 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Ludovic Henry <git@ludovic.dev>
+Date: Thu, 03 Sep 2026 00:00:00 +0000
+Subject: [PATCH] lance-linalg: add a portable riscv64 SIMD fallback
+
+lance-core's SIMD_SUPPORT static and lance-linalg's f32x8/f32x16/i32x8/
+f64x4/f64x8 SIMD types hardcode x86_64 (AVX/AVX2/AVX-512), aarch64
+(NEON) and loongarch64 (LSX/LASX) as the only supported architectures,
+with no portable fallback -- unlike u8x16/u8x32, which already carry
+one (rust/lance-linalg/src/simd/u8.rs). This adds the same shape of
+fallback for the missing types: an array-backed struct plus a scalar
+implementation of every method the SIMD/FloatSimd traits require, gated
+`#[cfg(not(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64")))]`
+beside the existing per-architecture arms, which are otherwise
+untouched. Add/Sub/Mul on i32x8 use wrapping arithmetic to match the
+silent-wraparound semantics of the SIMD instructions they replace.
+
+Verified with `cargo check --target riscv64gc-unknown-linux-gnu` (and,
+as a regression check, `--target aarch64-apple-darwin` and
+`--target x86_64-unknown-linux-gnu`) against an extracted copy of
+lance-linalg's simd module.
+
+Upstream-Status: To upstream [targets the lancedb/lance dependency rather than lancedb/lancedb itself; not yet submitted to lancedb/lance]
+
+Signed-off-by: Ludovic Henry <git@ludovic.dev>
+---
+ rust/lance-core/src/utils/cpu.rs  |   8 +
+ rust/lance-linalg/src/simd/f32.rs | 383 ++++++++++++++++++++++++++++++++++++++
+ rust/lance-linalg/src/simd/f64.rs | 364 ++++++++++++++++++++++++++++++++++++
+ rust/lance-linalg/src/simd/i32.rs | 176 ++++++++++++++++++
+ 4 files changed, 931 insertions(+)
+
+diff --git a/rust/lance-core/src/utils/cpu.rs b/rust/lance-core/src/utils/cpu.rs
+index c4d5a97..58adeb2 100644
+--- a/rust/lance-core/src/utils/cpu.rs
++++ b/rust/lance-core/src/utils/cpu.rs
+@@ -210,6 +210,14 @@ pub static SIMD_SUPPORT: LazyLock<SimdSupport> = LazyLock::new(|| {
+             SimdSupport::None
+         }
+     }
++    #[cfg(not(any(
++        target_arch = "aarch64",
++        target_arch = "x86_64",
++        target_arch = "loongarch64"
++    )))]
++    {
++        SimdSupport::None
++    }
+ });
+ 
+ #[cfg(target_arch = "x86_64")]
+diff --git a/rust/lance-linalg/src/simd/f32.rs b/rust/lance-linalg/src/simd/f32.rs
+index 4ce7f64..4e59e5f 100644
+--- a/rust/lance-linalg/src/simd/f32.rs
++++ b/rust/lance-linalg/src/simd/f32.rs
+@@ -35,6 +35,15 @@ pub struct f32x8(float32x4x2_t);
+ #[derive(Clone, Copy)]
+ pub struct f32x8(v8f32);
+ 
++#[allow(non_camel_case_types)]
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++#[derive(Clone, Copy)]
++pub struct f32x8([f32; 8]);
++
+ impl std::fmt::Debug for f32x8 {
+     fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result {
+         let mut arr = [0.0_f32; 8];
+@@ -45,6 +54,7 @@ impl std::fmt::Debug for f32x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl f32x8 {
+     /// Gather 8 f32 values from `slice` at the offsets in `indices`.
+     ///
+@@ -158,6 +168,7 @@ impl<'a> From<&'a [f32; 8]> for f32x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl SIMD<f32, 8> for f32x8 {
+     fn splat(val: f32) -> Self {
+         #[cfg(target_arch = "x86_64")]
+@@ -366,6 +377,7 @@ impl SIMD<f32, 8> for f32x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl FloatSimd<f32, 8> for f32x8 {
+     fn multiply_add(&mut self, a: Self, b: Self) {
+         #[cfg(target_arch = "x86_64")]
+@@ -384,6 +396,7 @@ impl FloatSimd<f32, 8> for f32x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl Add for f32x8 {
+     type Output = Self;
+ 
+@@ -407,6 +420,7 @@ impl Add for f32x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl AddAssign for f32x8 {
+     #[inline]
+     fn add_assign(&mut self, rhs: Self) {
+@@ -426,6 +440,7 @@ impl AddAssign for f32x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl Sub for f32x8 {
+     type Output = Self;
+ 
+@@ -449,6 +464,7 @@ impl Sub for f32x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl SubAssign for f32x8 {
+     #[inline]
+     fn sub_assign(&mut self, rhs: Self) {
+@@ -468,6 +484,7 @@ impl SubAssign for f32x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl Mul for f32x8 {
+     type Output = Self;
+ 
+@@ -516,6 +533,15 @@ pub struct f32x16(float32x4x4_t);
+ #[derive(Clone, Copy)]
+ pub struct f32x16(v8f32, v8f32);
+ 
++#[allow(non_camel_case_types)]
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++#[derive(Clone, Copy)]
++pub struct f32x16([f32; 16]);
++
+ impl std::fmt::Debug for f32x16 {
+     fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result {
+         let mut arr = [0.0_f32; 16];
+@@ -538,6 +564,7 @@ impl<'a> From<&'a [f32; 16]> for f32x16 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl SIMD<f32, 16> for f32x16 {
+     #[inline]
+     fn splat(val: f32) -> Self {
+@@ -785,6 +812,7 @@ impl SIMD<f32, 16> for f32x16 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl FloatSimd<f32, 16> for f32x16 {
+     #[inline]
+     fn multiply_add(&mut self, a: Self, b: Self) {
+@@ -808,6 +836,7 @@ impl FloatSimd<f32, 16> for f32x16 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl Add for f32x16 {
+     type Output = Self;
+ 
+@@ -833,6 +862,7 @@ impl Add for f32x16 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl AddAssign for f32x16 {
+     #[inline]
+     fn add_assign(&mut self, rhs: Self) {
+@@ -856,6 +886,7 @@ impl AddAssign for f32x16 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl Mul for f32x16 {
+     type Output = Self;
+ 
+@@ -881,6 +912,7 @@ impl Mul for f32x16 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl Sub for f32x16 {
+     type Output = Self;
+ 
+@@ -906,6 +938,7 @@ impl Sub for f32x16 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl SubAssign for f32x16 {
+     #[inline]
+     fn sub_assign(&mut self, rhs: Self) {
+@@ -929,6 +962,356 @@ impl SubAssign for f32x16 {
+     }
+ }
+ 
++
++// ---------------------------------------------------------------------------
++// Portable scalar fallback for architectures with no dedicated SIMD kernel
++// above (e.g. riscv64). Correctness-first, no intrinsics.
++// ---------------------------------------------------------------------------
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl f32x8 {
++    /// Gather 8 f32 values from `slice` at the offsets in `indices`.
++    ///
++    /// # Panics
++    ///
++    /// If any index is negative or lands outside `slice`.
++    #[inline]
++    pub fn gather(slice: &[f32], indices: &[i32; 8]) -> Self {
++        let values = indices.map(|i| slice[i as usize]);
++        unsafe { Self::load_unaligned(values.as_ptr()) }
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl SIMD<f32, 8> for f32x8 {
++    #[inline]
++    fn splat(val: f32) -> Self {
++        Self([val; 8])
++    }
++
++    #[inline]
++    fn zeros() -> Self {
++        Self([0.0; 8])
++    }
++
++    #[inline]
++    unsafe fn load(ptr: *const f32) -> Self {
++        unsafe { Self::load_unaligned(ptr) }
++    }
++
++    #[inline]
++    unsafe fn load_unaligned(ptr: *const f32) -> Self {
++        let mut arr = [0.0_f32; 8];
++        unsafe {
++            std::ptr::copy_nonoverlapping(ptr, arr.as_mut_ptr(), 8);
++        }
++        Self(arr)
++    }
++
++    #[inline]
++    unsafe fn store(&self, ptr: *mut f32) {
++        unsafe { self.store_unaligned(ptr) }
++    }
++
++    #[inline]
++    unsafe fn store_unaligned(&self, ptr: *mut f32) {
++        unsafe {
++            std::ptr::copy_nonoverlapping(self.0.as_ptr(), ptr, 8);
++        }
++    }
++
++    #[inline]
++    fn reduce_sum(&self) -> f32 {
++        self.0.iter().sum()
++    }
++
++    #[inline]
++    fn reduce_min(&self) -> f32 {
++        self.0.iter().copied().fold(f32::INFINITY, f32::min)
++    }
++
++    #[inline]
++    fn min(&self, rhs: &Self) -> Self {
++        let mut result = [0.0_f32; 8];
++        for i in 0..8 {
++            result[i] = self.0[i].min(rhs.0[i]);
++        }
++        Self(result)
++    }
++
++    #[inline]
++    fn find(&self, val: f32) -> Option<i32> {
++        self.0.iter().position(|&x| x == val).map(|i| i as i32)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl FloatSimd<f32, 8> for f32x8 {
++    #[inline]
++    fn multiply_add(&mut self, a: Self, b: Self) {
++        for i in 0..8 {
++            self.0[i] += a.0[i] * b.0[i];
++        }
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl Add for f32x8 {
++    type Output = Self;
++
++    #[inline]
++    fn add(self, rhs: Self) -> Self::Output {
++        let mut result = [0.0_f32; 8];
++        for i in 0..8 {
++            result[i] = self.0[i] + rhs.0[i];
++        }
++        Self(result)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl AddAssign for f32x8 {
++    #[inline]
++    fn add_assign(&mut self, rhs: Self) {
++        for i in 0..8 {
++            self.0[i] += rhs.0[i];
++        }
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl Sub for f32x8 {
++    type Output = Self;
++
++    #[inline]
++    fn sub(self, rhs: Self) -> Self::Output {
++        let mut result = [0.0_f32; 8];
++        for i in 0..8 {
++            result[i] = self.0[i] - rhs.0[i];
++        }
++        Self(result)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl SubAssign for f32x8 {
++    #[inline]
++    fn sub_assign(&mut self, rhs: Self) {
++        for i in 0..8 {
++            self.0[i] -= rhs.0[i];
++        }
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl Mul for f32x8 {
++    type Output = Self;
++
++    #[inline]
++    fn mul(self, rhs: Self) -> Self::Output {
++        let mut result = [0.0_f32; 8];
++        for i in 0..8 {
++            result[i] = self.0[i] * rhs.0[i];
++        }
++        Self(result)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl SIMD<f32, 16> for f32x16 {
++    #[inline]
++    fn splat(val: f32) -> Self {
++        Self([val; 16])
++    }
++
++    #[inline]
++    fn zeros() -> Self {
++        Self([0.0; 16])
++    }
++
++    #[inline]
++    unsafe fn load(ptr: *const f32) -> Self {
++        unsafe { Self::load_unaligned(ptr) }
++    }
++
++    #[inline]
++    unsafe fn load_unaligned(ptr: *const f32) -> Self {
++        let mut arr = [0.0_f32; 16];
++        unsafe {
++            std::ptr::copy_nonoverlapping(ptr, arr.as_mut_ptr(), 16);
++        }
++        Self(arr)
++    }
++
++    #[inline]
++    unsafe fn store(&self, ptr: *mut f32) {
++        unsafe { self.store_unaligned(ptr) }
++    }
++
++    #[inline]
++    unsafe fn store_unaligned(&self, ptr: *mut f32) {
++        unsafe {
++            std::ptr::copy_nonoverlapping(self.0.as_ptr(), ptr, 16);
++        }
++    }
++
++    #[inline]
++    fn reduce_sum(&self) -> f32 {
++        self.0.iter().sum()
++    }
++
++    #[inline]
++    fn reduce_min(&self) -> f32 {
++        self.0.iter().copied().fold(f32::INFINITY, f32::min)
++    }
++
++    #[inline]
++    fn min(&self, rhs: &Self) -> Self {
++        let mut result = [0.0_f32; 16];
++        for i in 0..16 {
++            result[i] = self.0[i].min(rhs.0[i]);
++        }
++        Self(result)
++    }
++
++    #[inline]
++    fn find(&self, val: f32) -> Option<i32> {
++        self.0.iter().position(|&x| x == val).map(|i| i as i32)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl FloatSimd<f32, 16> for f32x16 {
++    #[inline]
++    fn multiply_add(&mut self, a: Self, b: Self) {
++        for i in 0..16 {
++            self.0[i] += a.0[i] * b.0[i];
++        }
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl Add for f32x16 {
++    type Output = Self;
++
++    #[inline]
++    fn add(self, rhs: Self) -> Self::Output {
++        let mut result = [0.0_f32; 16];
++        for i in 0..16 {
++            result[i] = self.0[i] + rhs.0[i];
++        }
++        Self(result)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl AddAssign for f32x16 {
++    #[inline]
++    fn add_assign(&mut self, rhs: Self) {
++        for i in 0..16 {
++            self.0[i] += rhs.0[i];
++        }
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl Sub for f32x16 {
++    type Output = Self;
++
++    #[inline]
++    fn sub(self, rhs: Self) -> Self::Output {
++        let mut result = [0.0_f32; 16];
++        for i in 0..16 {
++            result[i] = self.0[i] - rhs.0[i];
++        }
++        Self(result)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl SubAssign for f32x16 {
++    #[inline]
++    fn sub_assign(&mut self, rhs: Self) {
++        for i in 0..16 {
++            self.0[i] -= rhs.0[i];
++        }
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl Mul for f32x16 {
++    type Output = Self;
++
++    #[inline]
++    fn mul(self, rhs: Self) -> Self::Output {
++        let mut result = [0.0_f32; 16];
++        for i in 0..16 {
++            result[i] = self.0[i] * rhs.0[i];
++        }
++        Self(result)
++    }
++}
++
+ #[cfg(test)]
+ mod tests {
+ 
+diff --git a/rust/lance-linalg/src/simd/f64.rs b/rust/lance-linalg/src/simd/f64.rs
+index 1276f54..88e74a6 100644
+--- a/rust/lance-linalg/src/simd/f64.rs
++++ b/rust/lance-linalg/src/simd/f64.rs
+@@ -33,6 +33,15 @@ pub struct f64x4(float64x2x2_t);
+ #[derive(Clone, Copy)]
+ pub struct f64x4(v4f64);
+ 
++#[allow(non_camel_case_types)]
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++#[derive(Clone, Copy)]
++pub struct f64x4([f64; 4]);
++
+ impl std::fmt::Debug for f64x4 {
+     fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result {
+         let mut arr = [0.0_f64; 4];
+@@ -55,6 +64,7 @@ impl<'a> From<&'a [f64; 4]> for f64x4 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl SIMD<f64, 4> for f64x4 {
+     fn splat(val: f64) -> Self {
+         #[cfg(target_arch = "x86_64")]
+@@ -226,6 +236,7 @@ impl SIMD<f64, 4> for f64x4 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl FloatSimd<f64, 4> for f64x4 {
+     fn multiply_add(&mut self, a: Self, b: Self) {
+         #[cfg(target_arch = "x86_64")]
+@@ -244,6 +255,7 @@ impl FloatSimd<f64, 4> for f64x4 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl Add for f64x4 {
+     type Output = Self;
+ 
+@@ -267,6 +279,7 @@ impl Add for f64x4 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl AddAssign for f64x4 {
+     #[inline]
+     fn add_assign(&mut self, rhs: Self) {
+@@ -286,6 +299,7 @@ impl AddAssign for f64x4 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl Sub for f64x4 {
+     type Output = Self;
+ 
+@@ -309,6 +323,7 @@ impl Sub for f64x4 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl SubAssign for f64x4 {
+     #[inline]
+     fn sub_assign(&mut self, rhs: Self) {
+@@ -328,6 +343,7 @@ impl SubAssign for f64x4 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl Mul for f64x4 {
+     type Output = Self;
+ 
+@@ -377,6 +393,15 @@ pub struct f64x8(float64x2x2_t, float64x2x2_t);
+ #[derive(Clone, Copy)]
+ pub struct f64x8(v4f64, v4f64);
+ 
++#[allow(non_camel_case_types)]
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++#[derive(Clone, Copy)]
++pub struct f64x8([f64; 8]);
++
+ impl std::fmt::Debug for f64x8 {
+     fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result {
+         let mut arr = [0.0_f64; 8];
+@@ -399,6 +424,7 @@ impl<'a> From<&'a [f64; 8]> for f64x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl SIMD<f64, 8> for f64x8 {
+     #[inline]
+     fn splat(val: f64) -> Self {
+@@ -592,6 +618,7 @@ impl SIMD<f64, 8> for f64x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl FloatSimd<f64, 8> for f64x8 {
+     #[inline]
+     fn multiply_add(&mut self, a: Self, b: Self) {
+@@ -615,6 +642,7 @@ impl FloatSimd<f64, 8> for f64x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl Add for f64x8 {
+     type Output = Self;
+ 
+@@ -638,6 +666,7 @@ impl Add for f64x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl AddAssign for f64x8 {
+     #[inline]
+     fn add_assign(&mut self, rhs: Self) {
+@@ -661,6 +690,7 @@ impl AddAssign for f64x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl Mul for f64x8 {
+     type Output = Self;
+ 
+@@ -684,6 +714,7 @@ impl Mul for f64x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl Sub for f64x8 {
+     type Output = Self;
+ 
+@@ -707,6 +738,7 @@ impl Sub for f64x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl SubAssign for f64x8 {
+     #[inline]
+     fn sub_assign(&mut self, rhs: Self) {
+@@ -730,6 +762,338 @@ impl SubAssign for f64x8 {
+     }
+ }
+ 
++
++// ---------------------------------------------------------------------------
++// Portable scalar fallback for architectures with no dedicated SIMD kernel
++// above (e.g. riscv64). Correctness-first, no intrinsics.
++// ---------------------------------------------------------------------------
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl SIMD<f64, 4> for f64x4 {
++    #[inline]
++    fn splat(val: f64) -> Self {
++        Self([val; 4])
++    }
++
++    #[inline]
++    fn zeros() -> Self {
++        Self([0.0; 4])
++    }
++
++    #[inline]
++    unsafe fn load(ptr: *const f64) -> Self {
++        unsafe { Self::load_unaligned(ptr) }
++    }
++
++    #[inline]
++    unsafe fn load_unaligned(ptr: *const f64) -> Self {
++        let mut arr = [0.0_f64; 4];
++        unsafe {
++            std::ptr::copy_nonoverlapping(ptr, arr.as_mut_ptr(), 4);
++        }
++        Self(arr)
++    }
++
++    #[inline]
++    unsafe fn store(&self, ptr: *mut f64) {
++        unsafe { self.store_unaligned(ptr) }
++    }
++
++    #[inline]
++    unsafe fn store_unaligned(&self, ptr: *mut f64) {
++        unsafe {
++            std::ptr::copy_nonoverlapping(self.0.as_ptr(), ptr, 4);
++        }
++    }
++
++    #[inline]
++    fn reduce_sum(&self) -> f64 {
++        self.0.iter().sum()
++    }
++
++    #[inline]
++    fn reduce_min(&self) -> f64 {
++        self.0.iter().copied().fold(f64::INFINITY, f64::min)
++    }
++
++    #[inline]
++    fn min(&self, rhs: &Self) -> Self {
++        let mut result = [0.0_f64; 4];
++        for i in 0..4 {
++            result[i] = self.0[i].min(rhs.0[i]);
++        }
++        Self(result)
++    }
++
++    #[inline]
++    fn find(&self, val: f64) -> Option<i32> {
++        self.0.iter().position(|&x| x == val).map(|i| i as i32)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl FloatSimd<f64, 4> for f64x4 {
++    #[inline]
++    fn multiply_add(&mut self, a: Self, b: Self) {
++        for i in 0..4 {
++            self.0[i] += a.0[i] * b.0[i];
++        }
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl Add for f64x4 {
++    type Output = Self;
++
++    #[inline]
++    fn add(self, rhs: Self) -> Self::Output {
++        let mut result = [0.0_f64; 4];
++        for i in 0..4 {
++            result[i] = self.0[i] + rhs.0[i];
++        }
++        Self(result)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl AddAssign for f64x4 {
++    #[inline]
++    fn add_assign(&mut self, rhs: Self) {
++        for i in 0..4 {
++            self.0[i] += rhs.0[i];
++        }
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl Sub for f64x4 {
++    type Output = Self;
++
++    #[inline]
++    fn sub(self, rhs: Self) -> Self::Output {
++        let mut result = [0.0_f64; 4];
++        for i in 0..4 {
++            result[i] = self.0[i] - rhs.0[i];
++        }
++        Self(result)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl SubAssign for f64x4 {
++    #[inline]
++    fn sub_assign(&mut self, rhs: Self) {
++        for i in 0..4 {
++            self.0[i] -= rhs.0[i];
++        }
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl Mul for f64x4 {
++    type Output = Self;
++
++    #[inline]
++    fn mul(self, rhs: Self) -> Self::Output {
++        let mut result = [0.0_f64; 4];
++        for i in 0..4 {
++            result[i] = self.0[i] * rhs.0[i];
++        }
++        Self(result)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl SIMD<f64, 8> for f64x8 {
++    #[inline]
++    fn splat(val: f64) -> Self {
++        Self([val; 8])
++    }
++
++    #[inline]
++    fn zeros() -> Self {
++        Self([0.0; 8])
++    }
++
++    #[inline]
++    unsafe fn load(ptr: *const f64) -> Self {
++        unsafe { Self::load_unaligned(ptr) }
++    }
++
++    #[inline]
++    unsafe fn load_unaligned(ptr: *const f64) -> Self {
++        let mut arr = [0.0_f64; 8];
++        unsafe {
++            std::ptr::copy_nonoverlapping(ptr, arr.as_mut_ptr(), 8);
++        }
++        Self(arr)
++    }
++
++    #[inline]
++    unsafe fn store(&self, ptr: *mut f64) {
++        unsafe { self.store_unaligned(ptr) }
++    }
++
++    #[inline]
++    unsafe fn store_unaligned(&self, ptr: *mut f64) {
++        unsafe {
++            std::ptr::copy_nonoverlapping(self.0.as_ptr(), ptr, 8);
++        }
++    }
++
++    #[inline]
++    fn reduce_sum(&self) -> f64 {
++        self.0.iter().sum()
++    }
++
++    #[inline]
++    fn reduce_min(&self) -> f64 {
++        self.0.iter().copied().fold(f64::INFINITY, f64::min)
++    }
++
++    #[inline]
++    fn min(&self, rhs: &Self) -> Self {
++        let mut result = [0.0_f64; 8];
++        for i in 0..8 {
++            result[i] = self.0[i].min(rhs.0[i]);
++        }
++        Self(result)
++    }
++
++    #[inline]
++    fn find(&self, val: f64) -> Option<i32> {
++        self.0.iter().position(|&x| x == val).map(|i| i as i32)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl FloatSimd<f64, 8> for f64x8 {
++    #[inline]
++    fn multiply_add(&mut self, a: Self, b: Self) {
++        for i in 0..8 {
++            self.0[i] += a.0[i] * b.0[i];
++        }
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl Add for f64x8 {
++    type Output = Self;
++
++    #[inline]
++    fn add(self, rhs: Self) -> Self::Output {
++        let mut result = [0.0_f64; 8];
++        for i in 0..8 {
++            result[i] = self.0[i] + rhs.0[i];
++        }
++        Self(result)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl AddAssign for f64x8 {
++    #[inline]
++    fn add_assign(&mut self, rhs: Self) {
++        for i in 0..8 {
++            self.0[i] += rhs.0[i];
++        }
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl Sub for f64x8 {
++    type Output = Self;
++
++    #[inline]
++    fn sub(self, rhs: Self) -> Self::Output {
++        let mut result = [0.0_f64; 8];
++        for i in 0..8 {
++            result[i] = self.0[i] - rhs.0[i];
++        }
++        Self(result)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl SubAssign for f64x8 {
++    #[inline]
++    fn sub_assign(&mut self, rhs: Self) {
++        for i in 0..8 {
++            self.0[i] -= rhs.0[i];
++        }
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl Mul for f64x8 {
++    type Output = Self;
++
++    #[inline]
++    fn mul(self, rhs: Self) -> Self::Output {
++        let mut result = [0.0_f64; 8];
++        for i in 0..8 {
++            result[i] = self.0[i] * rhs.0[i];
++        }
++        Self(result)
++    }
++}
++
+ #[cfg(test)]
+ mod tests {
+     use super::*;
+diff --git a/rust/lance-linalg/src/simd/i32.rs b/rust/lance-linalg/src/simd/i32.rs
+index fa8cdaf..2f14b9c 100644
+--- a/rust/lance-linalg/src/simd/i32.rs
++++ b/rust/lance-linalg/src/simd/i32.rs
+@@ -30,6 +30,15 @@ pub struct i32x8(int32x4x2_t);
+ #[derive(Clone, Copy)]
+ pub struct i32x8(v8i32);
+ 
++#[allow(non_camel_case_types)]
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++#[derive(Clone, Copy)]
++pub struct i32x8([i32; 8]);
++
+ impl std::fmt::Debug for i32x8 {
+     fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result {
+         let mut arr = [0; 8];
+@@ -52,6 +61,7 @@ impl From<&[i32; 8]> for i32x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl SIMD<i32, 8> for i32x8 {
+     #[inline]
+     fn splat(val: i32) -> Self {
+@@ -210,6 +220,7 @@ impl SIMD<i32, 8> for i32x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl Add for i32x8 {
+     type Output = Self;
+ 
+@@ -233,6 +244,7 @@ impl Add for i32x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl AddAssign for i32x8 {
+     #[inline]
+     fn add_assign(&mut self, rhs: Self) {
+@@ -252,6 +264,7 @@ impl AddAssign for i32x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl Sub for i32x8 {
+     type Output = Self;
+ 
+@@ -275,6 +288,7 @@ impl Sub for i32x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl SubAssign for i32x8 {
+     #[inline]
+     fn sub_assign(&mut self, rhs: Self) {
+@@ -294,6 +308,7 @@ impl SubAssign for i32x8 {
+     }
+ }
+ 
++#[cfg(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "loongarch64"))]
+ impl Mul for i32x8 {
+     type Output = Self;
+ 
+@@ -317,5 +332,166 @@ impl Mul for i32x8 {
+     }
+ }
+ 
++
++// ---------------------------------------------------------------------------
++// Portable scalar fallback for architectures with no dedicated SIMD kernel
++// above (e.g. riscv64). Correctness-first, no intrinsics. Add/Sub/Mul use
++// wrapping arithmetic to mirror the silent-wraparound semantics of the
++// `_mm256_{add,sub,mul}_epi32` / `vaddq_s32` / `lasx_xv{add,sub,mul}_w`
++// instructions above.
++// ---------------------------------------------------------------------------
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl SIMD<i32, 8> for i32x8 {
++    #[inline]
++    fn splat(val: i32) -> Self {
++        Self([val; 8])
++    }
++
++    #[inline]
++    fn zeros() -> Self {
++        Self([0; 8])
++    }
++
++    #[inline]
++    unsafe fn load(ptr: *const i32) -> Self {
++        unsafe { Self::load_unaligned(ptr) }
++    }
++
++    #[inline]
++    unsafe fn load_unaligned(ptr: *const i32) -> Self {
++        let mut arr = [0_i32; 8];
++        unsafe {
++            std::ptr::copy_nonoverlapping(ptr, arr.as_mut_ptr(), 8);
++        }
++        Self(arr)
++    }
++
++    #[inline]
++    unsafe fn store(&self, ptr: *mut i32) {
++        unsafe { self.store_unaligned(ptr) }
++    }
++
++    #[inline]
++    unsafe fn store_unaligned(&self, ptr: *mut i32) {
++        unsafe {
++            std::ptr::copy_nonoverlapping(self.0.as_ptr(), ptr, 8);
++        }
++    }
++
++    #[inline]
++    fn reduce_sum(&self) -> i32 {
++        self.0.iter().sum()
++    }
++
++    #[inline]
++    fn reduce_min(&self) -> i32 {
++        todo!()
++    }
++
++    #[inline]
++    fn min(&self, rhs: &Self) -> Self {
++        let mut result = [0_i32; 8];
++        for i in 0..8 {
++            result[i] = std::cmp::min(self.0[i], rhs.0[i]);
++        }
++        Self(result)
++    }
++
++    #[inline]
++    fn find(&self, val: i32) -> Option<i32> {
++        self.0
++            .iter()
++            .position(|&x| x == val)
++            .map(|i| i as i32)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl Add for i32x8 {
++    type Output = Self;
++
++    #[inline]
++    fn add(self, rhs: Self) -> Self::Output {
++        let mut result = [0_i32; 8];
++        for i in 0..8 {
++            result[i] = self.0[i].wrapping_add(rhs.0[i]);
++        }
++        Self(result)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl AddAssign for i32x8 {
++    #[inline]
++    fn add_assign(&mut self, rhs: Self) {
++        for i in 0..8 {
++            self.0[i] = self.0[i].wrapping_add(rhs.0[i]);
++        }
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl Sub for i32x8 {
++    type Output = Self;
++
++    #[inline]
++    fn sub(self, rhs: Self) -> Self::Output {
++        let mut result = [0_i32; 8];
++        for i in 0..8 {
++            result[i] = self.0[i].wrapping_sub(rhs.0[i]);
++        }
++        Self(result)
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl SubAssign for i32x8 {
++    #[inline]
++    fn sub_assign(&mut self, rhs: Self) {
++        for i in 0..8 {
++            self.0[i] = self.0[i].wrapping_sub(rhs.0[i]);
++        }
++    }
++}
++
++#[cfg(not(any(
++    target_arch = "x86_64",
++    target_arch = "aarch64",
++    target_arch = "loongarch64"
++)))]
++impl Mul for i32x8 {
++    type Output = Self;
++
++    #[inline]
++    fn mul(self, rhs: Self) -> Self::Output {
++        let mut result = [0_i32; 8];
++        for i in 0..8 {
++            result[i] = self.0[i].wrapping_mul(rhs.0[i]);
++        }
++        Self(result)
++    }
++}
++
+ #[cfg(test)]
+ mod tests {}
+-- 
+2.43.0