diff --git a/RTE/_Debug_SSE-320-U85/Pre_Include_Global.h b/RTE/_Debug_SSE-320-U85/Pre_Include_Global.h new file mode 100644 index 00000000..d7167599 --- /dev/null +++ b/RTE/_Debug_SSE-320-U85/Pre_Include_Global.h @@ -0,0 +1,25 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.14.1+p38-gf512b381 + * + * Project: 'cmsis-executorch-simple.Debug+SSE-320-U85' + * Target: 'Debug+SSE-320-U85' + */ + +#ifndef PRE_INCLUDE_GLOBAL_H +#define PRE_INCLUDE_GLOBAL_H + +/* ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U85@1.25.2 */ +// enabling global pre includes + #define ETHOSU_ARCH u85 +/* PyTorch::Machine Learning:ExecuTorch:Backend EthosU@1.4.0 */ +#define EXECUTORCH_BUILD_ARM_BAREMETAL 1 + #define ET_USE_ETHOS_U_BACKEND 1 +/* PyTorch::Machine Learning:ExecuTorch:Runtime@1.4.0 */ +/* ExecuTorch global configuration */ + #define C10_USING_CUSTOM_GENERATED_MACROS + #define FLATBUFFERS_MAX_ALIGNMENT 1024 + #define FLATBUFFERS_LOCALE_INDEPENDENT 0 + + +#endif /* PRE_INCLUDE_GLOBAL_H */ diff --git a/RTE/_Debug_SSE-320-U85/RTE_Components.h b/RTE/_Debug_SSE-320-U85/RTE_Components.h new file mode 100644 index 00000000..1faf7965 --- /dev/null +++ b/RTE/_Debug_SSE-320-U85/RTE_Components.h @@ -0,0 +1,49 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.14.1+p38-gf512b381 + * + * Project: 'cmsis-executorch-simple.Debug+SSE-320-U85' + * Target: 'Debug+SSE-320-U85' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE320.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ +#define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ +#define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ +#define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::Device:Native Driver:SysCounter@1.0.1 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.1 */ +#define RTE_TIMEOUT 1 +/* ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U85@1.25.2 */ +#define RTE_ETHOS_U_CORE_DRIVER +/* PyTorch::Machine Learning:ExecuTorch Operators:Quantized dequantize@1.4.0 */ +#define RTE_ML_EXECUTORCH_OP_QUANTIZED_DEQUANTIZE /* ExecuTorch op_dequantize */ +/* PyTorch::Machine Learning:ExecuTorch Operators:Quantized quantize@1.4.0 */ +#define RTE_ML_EXECUTORCH_OP_QUANTIZED_QUANTIZE /* ExecuTorch op_quantize */ +/* PyTorch::Machine Learning:ExecuTorch:Backend EthosU@1.4.0 */ +#define RTE_ML_EXECUTORCH_BACKEND_ETHOS_U /* ExecuTorch Ethos-U Backend (Cortex-M host) */ +/* PyTorch::Machine Learning:ExecuTorch:Extension Tensor@1.4.0 */ +#define RTE_ML_EXECUTORCH_EXTENSION_TENSOR /* ExecuTorch Tensor Extension */ +/* PyTorch::Machine Learning:ExecuTorch:Kernel Registration@1.4.0 */ +#define RTE_ML_EXECUTORCH_KERNEL_REGISTRATION /* ExecuTorch Kernel Registration */ +/* PyTorch::Machine Learning:ExecuTorch:Kernel Utils@1.4.0 */ +#define RTE_ML_EXECUTORCH_KERNEL_UTILS /* ExecuTorch Kernel Utils */ +/* PyTorch::Machine Learning:ExecuTorch:Runtime@1.4.0 */ +#define RTE_ML_EXECUTORCH_RUNTIME /* ExecuTorch Runtime */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ai_layer/ai_layer.clayer.yml b/ai_layer/ai_layer.clayer.yml index 84a586b6..12bfcbb8 100644 --- a/ai_layer/ai_layer.clayer.yml +++ b/ai_layer/ai_layer.clayer.yml @@ -15,6 +15,7 @@ layer: - component: Machine Learning:ExecuTorch:Runtime - component: Machine Learning:ExecuTorch:Kernel Utils - component: Machine Learning:ExecuTorch:Kernel Registration + - component: Machine Learning:ExecuTorch:Extension Tensor # Ethos-U NPU backend (the model is fully delegated to it). - component: Machine Learning:ExecuTorch:Backend EthosU # Quantized reference operators. diff --git a/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src b/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src new file mode 100644 index 00000000..7820e1f1 --- /dev/null +++ b/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE 8 +#else +#define __STACKSEAL_SIZE 0 +#endif + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +LR_ROM0 __ROM0_BASE __ROM0_SIZE { + + ER_ROM0 __ROM0_BASE __ROM0_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + *(+RO +XO) + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) { + *(Veneer$$CMSE) + } +#endif + + RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { + *.o(.bss.noinit) + *.o(.bss.noinit.*) + } + + RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if __STACKSEAL_SIZE > 0 + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif + +#if __RAM1_SIZE > 0 + RW_RAM1 __RAM1_BASE __RAM1_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM2_SIZE > 0 + RW_RAM2 __RAM2_BASE __RAM2_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM3_SIZE > 0 + RW_RAM3 __RAM3_BASE __RAM3_SIZE { + .ANY (+RW +ZI) + } +#endif +} + +#if __ROM1_SIZE > 0 +LR_ROM1 __ROM1_BASE __ROM1_SIZE { + ER_ROM1 +0 __ROM1_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM2_SIZE > 0 +LR_ROM2 __ROM2_BASE __ROM2_SIZE { + ER_ROM2 +0 __ROM2_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM3_SIZE > 0 +LR_ROM3 __ROM3_BASE __ROM3_SIZE { + ER_ROM3 +0 __ROM3_SIZE { + .ANY (+RO +XO) + } +} +#endif diff --git a/board/Corstone-320/RTE/Device/SSE-320-FVP/device_cfg.h b/board/Corstone-320/RTE/Device/SSE-320-FVP/device_cfg.h new file mode 100644 index 00000000..19e2c883 --- /dev/null +++ b/board/Corstone-320/RTE/Device/SSE-320-FVP/device_cfg.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2020-2024 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif +#ifdef RTE_I2C1 +#define I2C1_SBCON_S +#define I2C1_SBCON_DEV I2C1_SBCON_DEV_S +#endif +#ifdef RTE_I2C2 +#define I2C2_SBCON_S +#define I2C2_SBCON_DEV I2C2_SBCON_DEV_S +#endif +#ifdef RTE_I2C3 +#define I2C3_SBCON_S +#define I2C3_SBCON_DEV I2C3_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif +#ifdef RTE_USART2 +#define UART2_CMSDK_S +#define UART2_CMSDK_DEV UART2_CMSDK_DEV_S +#endif +#ifdef RTE_USART3 +#define UART3_CMSDK_S +#define UART3_CMSDK_DEV UART3_CMSDK_DEV_S +#endif +#ifdef RTE_USART4 +#define UART4_CMSDK_S +#define UART4_CMSDK_DEV UART4_CMSDK_DEV_S +#endif +#ifdef RTE_USART5 +#define UART5_CMSDK_S +#define UART5_CMSDK_DEV UART5_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 320 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE320 +#define PPC_CORSTONE320_MAIN0_S +#define PPC_CORSTONE320_MAIN0_DEV PPC_CORSTONE320_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE320 +#define PPC_CORSTONE320_MAIN_EXP0_S +#define PPC_CORSTONE320_MAIN_EXP0_DEV PPC_CORSTONE320_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE320 +#define PPC_CORSTONE320_MAIN_EXP1_S +#define PPC_CORSTONE320_MAIN_EXP1_DEV PPC_CORSTONE320_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE320 +#define PPC_CORSTONE320_MAIN_EXP2_S +#define PPC_CORSTONE320_MAIN_EXP2_DEV PPC_CORSTONE320_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE320 +#define PPC_CORSTONE320_MAIN_EXP3_S +#define PPC_CORSTONE320_MAIN_EXP3_DEV PPC_CORSTONE320_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE320 +#define PPC_CORSTONE320_PERIPH0_S +#define PPC_CORSTONE320_PERIPH0_DEV PPC_CORSTONE320_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE320 +#define PPC_CORSTONE320_PERIPH1_S +#define PPC_CORSTONE320_PERIPH1_DEV PPC_CORSTONE320_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE320 +#define PPC_CORSTONE320_PERIPH_EXP0_S +#define PPC_CORSTONE320_PERIPH_EXP0_DEV PPC_CORSTONE320_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE320 +#define PPC_CORSTONE320_PERIPH_EXP1_S +#define PPC_CORSTONE320_PERIPH_EXP1_DEV PPC_CORSTONE320_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE320 +#define PPC_CORSTONE320_PERIPH_EXP2_S +#define PPC_CORSTONE320_PERIPH_EXP2_DEV PPC_CORSTONE320_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE320 +#define PPC_CORSTONE320_PERIPH_EXP3_S +#define PPC_CORSTONE320_PERIPH_EXP3_DEV PPC_CORSTONE320_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* Key Management Unit */ +#ifdef RTE_KMU +#define KMU_S +#define KMU_DEV KMU_DEV_S +#endif + +/* Lifecycle Manager */ +#ifdef RTE_LCM +#define LCM_S +#define LCM_DEV LCM_DEV_S +#endif + +/* Security Alarm Manager */ +#ifdef RTE_SAM +#define SAM_S +#define SAM_DEV SAM_DEV_S +#endif + +/* HDLCD Video */ +#ifdef RTE_HDLCD +#define HDLCD_NS +#define HDLCD_DEV HDLCD_DEV_NS +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI0 +#define SPI0_PL022_S +#define SPI0_PL022_DEV SPI0_PL022_DEV_S +#endif +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif +#ifdef RTE_SPI2 +#define SPI2_PL022_S +#define SPI2_PL022_DEV SPI2_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/board/Corstone-320/RTE/Device/SSE-320-FVP/device_cfg.h.base@1.1.0 b/board/Corstone-320/RTE/Device/SSE-320-FVP/device_cfg.h.base@1.1.0 new file mode 100644 index 00000000..19e2c883 --- /dev/null +++ b/board/Corstone-320/RTE/Device/SSE-320-FVP/device_cfg.h.base@1.1.0 @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2020-2024 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +#include "RTE_Components.h" + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#ifdef RTE_MPS3_IO +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S +#endif + +/* I2C_SBCon */ +#ifdef RTE_I2C0 +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S +#endif +#ifdef RTE_I2C1 +#define I2C1_SBCON_S +#define I2C1_SBCON_DEV I2C1_SBCON_DEV_S +#endif +#ifdef RTE_I2C2 +#define I2C2_SBCON_S +#define I2C2_SBCON_DEV I2C2_SBCON_DEV_S +#endif +#ifdef RTE_I2C3 +#define I2C3_SBCON_S +#define I2C3_SBCON_DEV I2C3_SBCON_DEV_S +#endif + +/* I2S */ +#ifdef RTE_I2S +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S +#endif + +/* ARM UART Controller CMSDK */ +#ifdef RTE_USART0 +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#endif +#ifdef RTE_USART1 +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S +#endif +#ifdef RTE_USART2 +#define UART2_CMSDK_S +#define UART2_CMSDK_DEV UART2_CMSDK_DEV_S +#endif +#ifdef RTE_USART3 +#define UART3_CMSDK_S +#define UART3_CMSDK_DEV UART3_CMSDK_DEV_S +#endif +#ifdef RTE_USART4 +#define UART4_CMSDK_S +#define UART4_CMSDK_DEV UART4_CMSDK_DEV_S +#endif +#ifdef RTE_USART5 +#define UART5_CMSDK_S +#define UART5_CMSDK_DEV UART5_CMSDK_DEV_S +#endif + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#ifdef RTE_ISRAM0_MPC +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_ISRAM1_MPC +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S +#endif + +#ifdef RTE_SRAM_MPC +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S +#endif + +#ifdef RTE_QSPI_MPC +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S +#endif + +/** System Counter Armv8-M */ +#ifdef RTE_SYSCOUNTER +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u +#endif + +/* System timer */ +#ifdef RTE_TIMEOUT +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) +#endif + +/* CMSDK GPIO driver structures */ +#ifdef RTE_GPIO +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S +#endif + +/* System Watchdogs */ +#ifdef RTE_WATCHDOG +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S +#endif + +/* ARM MPC SIE 320 driver structures */ +#ifdef RTE_VM0_MPC +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#endif +#ifdef RTE_VM1_MPC +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#endif +#ifdef RTE_SSRAM2_MPC +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#endif +#ifdef RTE_SSRAM3_MPC +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S +#endif + +/* ARM PPC driver structures */ +#ifdef RTE_MAIN0_PPC_CORSTONE320 +#define PPC_CORSTONE320_MAIN0_S +#define PPC_CORSTONE320_MAIN0_DEV PPC_CORSTONE320_MAIN0_DEV_S +#endif +#ifdef RTE_MAIN_EXP0_PPC_CORSTONE320 +#define PPC_CORSTONE320_MAIN_EXP0_S +#define PPC_CORSTONE320_MAIN_EXP0_DEV PPC_CORSTONE320_MAIN_EXP0_DEV_S +#endif +#ifdef RTE_MAIN_EXP1_PPC_CORSTONE320 +#define PPC_CORSTONE320_MAIN_EXP1_S +#define PPC_CORSTONE320_MAIN_EXP1_DEV PPC_CORSTONE320_MAIN_EXP1_DEV_S +#endif +#ifdef RTE_MAIN_EXP2_PPC_CORSTONE320 +#define PPC_CORSTONE320_MAIN_EXP2_S +#define PPC_CORSTONE320_MAIN_EXP2_DEV PPC_CORSTONE320_MAIN_EXP2_DEV_S +#endif +#ifdef RTE_MAIN_EXP3_PPC_CORSTONE320 +#define PPC_CORSTONE320_MAIN_EXP3_S +#define PPC_CORSTONE320_MAIN_EXP3_DEV PPC_CORSTONE320_MAIN_EXP3_DEV_S +#endif +#ifdef RTE_PERIPH0_PPC_CORSTONE320 +#define PPC_CORSTONE320_PERIPH0_S +#define PPC_CORSTONE320_PERIPH0_DEV PPC_CORSTONE320_PERIPH0_DEV_S +#endif +#ifdef RTE_PERIPH1_PPC_CORSTONE320 +#define PPC_CORSTONE320_PERIPH1_S +#define PPC_CORSTONE320_PERIPH1_DEV PPC_CORSTONE320_PERIPH1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP0_PPC_CORSTONE320 +#define PPC_CORSTONE320_PERIPH_EXP0_S +#define PPC_CORSTONE320_PERIPH_EXP0_DEV PPC_CORSTONE320_PERIPH_EXP0_DEV_S +#endif +#ifdef RTE_PERIPH_EXP1_PPC_CORSTONE320 +#define PPC_CORSTONE320_PERIPH_EXP1_S +#define PPC_CORSTONE320_PERIPH_EXP1_DEV PPC_CORSTONE320_PERIPH_EXP1_DEV_S +#endif +#ifdef RTE_PERIPH_EXP2_PPC_CORSTONE320 +#define PPC_CORSTONE320_PERIPH_EXP2_S +#define PPC_CORSTONE320_PERIPH_EXP2_DEV PPC_CORSTONE320_PERIPH_EXP2_DEV_S +#endif +#ifdef RTE_PERIPH_EXP3_PPC_CORSTONE320 +#define PPC_CORSTONE320_PERIPH_EXP3_S +#define PPC_CORSTONE320_PERIPH_EXP3_DEV PPC_CORSTONE320_PERIPH_EXP3_DEV_S +#endif + +/* DMA350 */ +#ifdef RTE_DMA350 +#define DMA350_DMA0_S +#define DMA350_DMA0_DEV DMA350_DMA0_DEV_S + +#define DMA350_CH0_S +#define DMA350_DMA0_CH0_S +#define DMA350_CH1_S +#define DMA350_DMA0_CH1_S +#endif + +/* Key Management Unit */ +#ifdef RTE_KMU +#define KMU_S +#define KMU_DEV KMU_DEV_S +#endif + +/* Lifecycle Manager */ +#ifdef RTE_LCM +#define LCM_S +#define LCM_DEV LCM_DEV_S +#endif + +/* Security Alarm Manager */ +#ifdef RTE_SAM +#define SAM_S +#define SAM_DEV SAM_DEV_S +#endif + +/* HDLCD Video */ +#ifdef RTE_HDLCD +#define HDLCD_NS +#define HDLCD_DEV HDLCD_DEV_NS +#endif + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#ifdef RTE_SPI0 +#define SPI0_PL022_S +#define SPI0_PL022_DEV SPI0_PL022_DEV_S +#endif +#ifdef RTE_SPI1 +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S +#endif +#ifdef RTE_SPI2 +#define SPI2_PL022_S +#define SPI2_PL022_DEV SPI2_PL022_DEV_S +#endif + +#endif /* __DEVICE_CFG_H__ */ diff --git a/board/Corstone-320/RTE/Device/SSE-320-FVP/startup_SSE320.c b/board/Corstone-320/RTE/Device/SSE-320-FVP/startup_SSE320.c new file mode 100644 index 00000000..2caeffa5 --- /dev/null +++ b/board/Corstone-320/RTE/Device/SSE-320-FVP/startup_SSE320.c @@ -0,0 +1,410 @@ +/* + * Copyright (c) 2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE320.h" +#include "system_SSE320.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +__NO_RETURN void __WEAK handler_name(void); \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(SDC_Handler) +DEFAULT_IRQ_HANDLER(KMU_Handler) +DEFAULT_IRQ_HANDLER(DMA_SEC_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_NONSEC_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_SECURITY_VIOLATION_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) +DEFAULT_IRQ_HANDLER(SAM_Critical_Severity_Fault_Handler) +DEFAULT_IRQ_HANDLER(SAM_Severity_Fault_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +DEFAULT_IRQ_HANDLER(NPU0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(RTC_Handler) +DEFAULT_IRQ_HANDLER(ISP_C55_Handler) +DEFAULT_IRQ_HANDLER(HDLCD_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI0_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI1_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI2_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI3_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI4_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI5_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI6_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI7_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + SDC_Handler, /* 15: Secure Debug Channel Handler */ + NPU0_Handler, /* 16: NPU0 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + KMU_Handler, /* 20: KMU Handler */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + DMA_SEC_Combined_Handler, /* 24: DMA Secure Combined Handler */ + DMA_NONSEC_Combined_Handler, /* 25: DMA Non-Secure Combined Handler */ + DMA_SECURITY_VIOLATION_Handler, /* 26: DMA Security Violation Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + SAM_Critical_Severity_Fault_Handler, /* 30: SAM Critical Severity Fault Handler */ + SAM_Severity_Fault_Handler, /* 31: SAM Severity Fault Handler */ + + /* External interrupts */ + 0, /* 32: Reserved */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + 0, /* 51: Reserved */ + 0, /* 52: Reserved */ + 0, /* 53: Reserved */ + 0, /* 54: Reserved */ + 0, /* 55: Reserved */ + 0, /* 56: Reserved */ + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + 0, /* 73: Reserved */ + 0, /* 74: Reserved */ + 0, /* 75: Reserved */ + 0, /* 76: Reserved */ + 0, /* 77: Reserved */ + 0, /* 78: Reserved */ + 0, /* 79: Reserved */ + 0, /* 80: Reserved */ + 0, /* 81: Reserved */ + 0, /* 82: Reserved */ + 0, /* 83: Reserved */ + 0, /* 84: Reserved */ + 0, /* 85: Reserved */ + 0, /* 86: Reserved */ + 0, /* 87: Reserved */ + 0, /* 88: Reserved */ + 0, /* 89: Reserved */ + 0, /* 90: Reserved */ + 0, /* 91: Reserved */ + 0, /* 92: Reserved */ + 0, /* 93: Reserved */ + 0, /* 94: Reserved */ + 0, /* 95: Reserved */ + 0, /* 96: Reserved */ + 0, /* 97: Reserved */ + 0, /* 98: Reserved */ + 0, /* 99: Reserved */ + 0, /* 100: Reserved */ + 0, /* 101: Reserved */ + 0, /* 102: Reserved */ + 0, /* 103: Reserved */ + 0, /* 104: Reserved */ + 0, /* 105: Reserved */ + 0, /* 106: Reserved */ + 0, /* 107: Reserved */ + 0, /* 108: Reserved */ + 0, /* 109: Reserved */ + 0, /* 110: Reserved */ + 0, /* 111: Reserved */ + 0, /* 112: Reserved */ + 0, /* 113: Reserved */ + 0, /* 114: Reserved */ + 0, /* 115: Reserved */ + 0, /* 116: Reserved */ + 0, /* 117: Reserved */ + 0, /* 118: Reserved */ + 0, /* 119: Reserved */ + 0, /* 120: Reserved */ + 0, /* 121: Reserved */ + 0, /* 122: Reserved */ + 0, /* 123: Reserved */ + 0, /* 124: Reserved */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + 0, /* 127: Reserved */ + RTC_Handler, /* 128: UART 5 combined Interrupt */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + ISP_C55_Handler, /* 132: ISP C55 Handler */ + HDLCD_Handler, /* 133: HDLCD Handler */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + ARM_VSI0_Handler, /* 224: VSI 0 Handler */ + ARM_VSI1_Handler, /* 225: VSI 1 Handler */ + ARM_VSI2_Handler, /* 226: VSI 2 Handler */ + ARM_VSI3_Handler, /* 227: VSI 3 Handler */ + ARM_VSI4_Handler, /* 228: VSI 4 Handler */ + ARM_VSI5_Handler, /* 229: VSI 5 Handler */ + ARM_VSI6_Handler, /* 230: VSI 6 Handler */ + ARM_VSI7_Handler, /* 231: VSI 7 Handler */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/board/Corstone-320/RTE/Device/SSE-320-FVP/startup_SSE320.c.base@1.1.0 b/board/Corstone-320/RTE/Device/SSE-320-FVP/startup_SSE320.c.base@1.1.0 new file mode 100644 index 00000000..2caeffa5 --- /dev/null +++ b/board/Corstone-320/RTE/Device/SSE-320-FVP/startup_SSE320.c.base@1.1.0 @@ -0,0 +1,410 @@ +/* + * Copyright (c) 2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE320.h" +#include "system_SSE320.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +__NO_RETURN void __WEAK handler_name(void); \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(COMBINED_PPU_Handler) +DEFAULT_IRQ_HANDLER(SDC_Handler) +DEFAULT_IRQ_HANDLER(KMU_Handler) +DEFAULT_IRQ_HANDLER(DMA_SEC_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_NONSEC_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_SECURITY_VIOLATION_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) +DEFAULT_IRQ_HANDLER(SAM_Critical_Severity_Fault_Handler) +DEFAULT_IRQ_HANDLER(SAM_Severity_Fault_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_0_Handler) +DEFAULT_IRQ_HANDLER(DMA_Channel_1_Handler) +DEFAULT_IRQ_HANDLER(NPU0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(RTC_Handler) +DEFAULT_IRQ_HANDLER(ISP_C55_Handler) +DEFAULT_IRQ_HANDLER(HDLCD_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI0_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI1_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI2_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI3_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI4_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI5_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI6_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI7_Handler) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + COMBINED_PPU_Handler, /* 14: Combined PPU Handler */ + SDC_Handler, /* 15: Secure Debug Channel Handler */ + NPU0_Handler, /* 16: NPU0 Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + KMU_Handler, /* 20: KMU Handler */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + DMA_SEC_Combined_Handler, /* 24: DMA Secure Combined Handler */ + DMA_NONSEC_Combined_Handler, /* 25: DMA Non-Secure Combined Handler */ + DMA_SECURITY_VIOLATION_Handler, /* 26: DMA Security Violation Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + SAM_Critical_Severity_Fault_Handler, /* 30: SAM Critical Severity Fault Handler */ + SAM_Severity_Fault_Handler, /* 31: SAM Severity Fault Handler */ + + /* External interrupts */ + 0, /* 32: Reserved */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + 0, /* 51: Reserved */ + 0, /* 52: Reserved */ + 0, /* 53: Reserved */ + 0, /* 54: Reserved */ + 0, /* 55: Reserved */ + 0, /* 56: Reserved */ + DMA_Channel_0_Handler, /* 57: DMA (DMA350) Channel 0 Handler */ + DMA_Channel_1_Handler, /* 58: DMA (DMA350) Channel 1 Handler */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + 0, /* 73: Reserved */ + 0, /* 74: Reserved */ + 0, /* 75: Reserved */ + 0, /* 76: Reserved */ + 0, /* 77: Reserved */ + 0, /* 78: Reserved */ + 0, /* 79: Reserved */ + 0, /* 80: Reserved */ + 0, /* 81: Reserved */ + 0, /* 82: Reserved */ + 0, /* 83: Reserved */ + 0, /* 84: Reserved */ + 0, /* 85: Reserved */ + 0, /* 86: Reserved */ + 0, /* 87: Reserved */ + 0, /* 88: Reserved */ + 0, /* 89: Reserved */ + 0, /* 90: Reserved */ + 0, /* 91: Reserved */ + 0, /* 92: Reserved */ + 0, /* 93: Reserved */ + 0, /* 94: Reserved */ + 0, /* 95: Reserved */ + 0, /* 96: Reserved */ + 0, /* 97: Reserved */ + 0, /* 98: Reserved */ + 0, /* 99: Reserved */ + 0, /* 100: Reserved */ + 0, /* 101: Reserved */ + 0, /* 102: Reserved */ + 0, /* 103: Reserved */ + 0, /* 104: Reserved */ + 0, /* 105: Reserved */ + 0, /* 106: Reserved */ + 0, /* 107: Reserved */ + 0, /* 108: Reserved */ + 0, /* 109: Reserved */ + 0, /* 110: Reserved */ + 0, /* 111: Reserved */ + 0, /* 112: Reserved */ + 0, /* 113: Reserved */ + 0, /* 114: Reserved */ + 0, /* 115: Reserved */ + 0, /* 116: Reserved */ + 0, /* 117: Reserved */ + 0, /* 118: Reserved */ + 0, /* 119: Reserved */ + 0, /* 120: Reserved */ + 0, /* 121: Reserved */ + 0, /* 122: Reserved */ + 0, /* 123: Reserved */ + 0, /* 124: Reserved */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + 0, /* 127: Reserved */ + RTC_Handler, /* 128: UART 5 combined Interrupt */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ + 0, /* 131: Reserved */ + ISP_C55_Handler, /* 132: ISP C55 Handler */ + HDLCD_Handler, /* 133: HDLCD Handler */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + ARM_VSI0_Handler, /* 224: VSI 0 Handler */ + ARM_VSI1_Handler, /* 225: VSI 1 Handler */ + ARM_VSI2_Handler, /* 226: VSI 2 Handler */ + ARM_VSI3_Handler, /* 227: VSI 3 Handler */ + ARM_VSI4_Handler, /* 228: VSI 4 Handler */ + ARM_VSI5_Handler, /* 229: VSI 5 Handler */ + ARM_VSI6_Handler, /* 230: VSI 6 Handler */ + ARM_VSI7_Handler, /* 231: VSI 7 Handler */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/board/Corstone-320/RTE/Device/SSE-320-FVP/system_SSE320.c b/board/Corstone-320/RTE/Device/SSE-320-FVP/system_SSE320.c new file mode 100644 index 00000000..9bb9a283 --- /dev/null +++ b/board/Corstone-320/RTE/Device/SSE-320-FVP/system_SSE320.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2009-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE320.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + /* Disable cache, because of BL2->Secure change. + If cache is enabled, then code decompression can fail or cause uncertain + behaviour after switching to main. + If cache needed to be Enabled before decompression, make sure to Clean + and Invalidate it at the begining of main(..)! + + If so, use: + SCB_InvalidateICache(); // I cache cannot be cleaned + SCB_CleanInvalidateDCache(); + */ + SCB_DisableICache(); + SCB_DisableDCache(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/board/Corstone-320/RTE/Device/SSE-320-FVP/system_SSE320.c.base@1.1.0 b/board/Corstone-320/RTE/Device/SSE-320-FVP/system_SSE320.c.base@1.1.0 new file mode 100644 index 00000000..9bb9a283 --- /dev/null +++ b/board/Corstone-320/RTE/Device/SSE-320-FVP/system_SSE320.c.base@1.1.0 @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2009-2024, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM85.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE320.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (25000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + + /* Disable cache, because of BL2->Secure change. + If cache is enabled, then code decompression can fail or cause uncertain + behaviour after switching to main. + If cache needed to be Enabled before decompression, make sure to Clean + and Invalidate it at the begining of main(..)! + + If so, use: + SCB_InvalidateICache(); // I cache cannot be cleaned + SCB_CleanInvalidateDCache(); + */ + SCB_DisableICache(); + SCB_DisableDCache(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/cmsis-executorch-simple.cproject.yml b/cmsis-executorch-simple.cproject.yml index 6a1e458a..7e9ad3a6 100644 --- a/cmsis-executorch-simple.cproject.yml +++ b/cmsis-executorch-simple.cproject.yml @@ -29,6 +29,8 @@ project: - group: App files: - file: ./src/app_main.cpp + - file: ./src/arm_embedded_module.cpp + - file: ./src/arm_embedded_module.hpp # Generated by the convert-model build step below. Listing it as a # project source makes CMSIS-Toolbox schedule that step BEFORE # compilation (a generated build input runs pre-build). diff --git a/scripts/gen_components.py b/scripts/gen_components.py index f1643e61..9218e8e7 100755 --- a/scripts/gen_components.py +++ b/scripts/gen_components.py @@ -140,6 +140,7 @@ def render(portable, quantized, cortex_m, pack_name, description) -> str: " - component: Machine Learning:ExecuTorch:Runtime", " - component: Machine Learning:ExecuTorch:Kernel Utils", " - component: Machine Learning:ExecuTorch:Kernel Registration", + " - component: Machine Learning:ExecuTorch:Extension Tensor", " # Ethos-U NPU backend (the model is fully delegated to it).", " - component: Machine Learning:ExecuTorch:Backend EthosU", ] diff --git a/src/app_main.cpp b/src/app_main.cpp index afabf2bd..ec5c1249 100644 --- a/src/app_main.cpp +++ b/src/app_main.cpp @@ -7,39 +7,29 @@ // PyTorch::ExecuTorch pack's runtime + operator components; the board layer // provides main(), stdout and the Ethos-U driver init and then calls app_main. // -// API usage mirrors backends/arm/.../test/all_ops/main.cpp. +// EmbeddedModule manages program loading, method memory, and execution. #include #include +#include +#include -#include -#include +#include +#include #include #include -#include #include -#include -#include -#include -#include -#include #include +#include "arm_embedded_module.hpp" #include "model_pte.h" +using arm::embedded::EmbeddedModule; using executorch::aten::Tensor; -using executorch::runtime::DataLoader; -using executorch::runtime::Error; +using executorch::extension::BufferDataLoader; +using executorch::extension::make_tensor_ptr; using executorch::runtime::EValue; -using executorch::runtime::FreeableBuffer; -using executorch::runtime::HierarchicalAllocator; using executorch::runtime::MemoryAllocator; -using executorch::runtime::MemoryManager; -using executorch::runtime::Method; -using executorch::runtime::MethodMeta; -using executorch::runtime::Program; -using executorch::runtime::Result; -using executorch::runtime::Span; namespace { @@ -49,27 +39,6 @@ constexpr size_t kTempPoolSize = 4 * 1024 * 1024; // Ethos-U scratch is drawn f alignas(16) uint8_t g_method_pool[kMethodPoolSize]; alignas(16) uint8_t g_temp_pool[kTempPoolSize]; -// In-memory DataLoader so we don't need the extension/data-loader tree. -class BufferLoader final : public DataLoader { - public: - BufferLoader(const void* data, size_t size) : data_(data), size_(size) {} - - Result load( - size_t offset, size_t size, const DataLoader::SegmentInfo&) const override { - if (offset + size > size_) { - return Error::InvalidArgument; - } - return FreeableBuffer( - static_cast(data_) + offset, size, nullptr); - } - - Result size() const override { return size_; } - - private: - const void* data_; - size_t size_; -}; - } // namespace extern "C" int app_main(void) { @@ -77,61 +46,32 @@ extern "C" int app_main(void) { printf("ExecuTorch Ethos-U85 example: %lu byte model\n", model_pte_size); - BufferLoader loader(model_pte, model_pte_size); - Result program = Program::load(&loader); - if (!program.ok()) { - printf("Program::load failed (err=%u)\n", static_cast(program.error())); - return 1; - } - - const char* method_name = "forward"; - Result meta = program->method_meta(method_name); - if (!meta.ok()) { - printf("method_meta failed\n"); - return 1; - } - - MemoryAllocator method_allocator(kMethodPoolSize, g_method_pool); - MemoryAllocator temp_allocator(kTempPoolSize, g_temp_pool); - - size_t num_planned = meta->num_memory_planned_buffers(); - Span planned_spans[8]; - for (size_t i = 0; i < num_planned && i < 8; ++i) { - size_t sz = meta->memory_planned_buffer_size(i).get(); - planned_spans[i] = {static_cast(method_allocator.allocate(sz, 16)), sz}; + EmbeddedModule module( + model_pte, model_pte_size, + std::make_unique(model_pte, model_pte_size), + std::make_unique(kMethodPoolSize, g_method_pool), + std::make_unique(kTempPoolSize, g_temp_pool)); + + // TinyCNN takes one 16x16 RGB image in NCHW order (see model/model.py). + // Keep the TensorPtr alive until forward() finishes using its data. + auto input = make_tensor_ptr( + {1, 3, 16, 16}, std::vector(3 * 16 * 16)); + float* input_data = input->mutable_data_ptr(); + for (size_t i = 0; i < input->numel(); ++i) { + input_data[i] = static_cast(i % 32) / 32.0f - 0.5f; } - HierarchicalAllocator planned_memory({planned_spans, num_planned}); - MemoryManager memory_manager(&method_allocator, &planned_memory, &temp_allocator); - Result method = program->load_method(method_name, &memory_manager); - if (!method.ok()) { - printf("load_method failed (err=%u)\n", static_cast(method.error())); + auto outputs = module.forward(*input); + if (!outputs.ok()) { + printf("forward failed (err=%u)\n", static_cast(outputs.error())); return 1; } - - // Fill each input tensor with a simple deterministic ramp. - for (size_t i = 0; i < method->inputs_size(); ++i) { - EValue in = method->get_input(i); - if (!in.isTensor()) { - continue; - } - Tensor t = in.toTensor(); - if (t.scalar_type() == executorch::aten::ScalarType::Float) { - float* p = t.mutable_data_ptr(); - size_t n = t.numel(); - for (size_t j = 0; j < n; ++j) { - p[j] = static_cast((j % 32)) / 32.0f - 0.5f; - } - } - } - - Error exec_err = method->execute(); - if (exec_err != Error::Ok) { - printf("execute failed (err=%u)\n", static_cast(exec_err)); + if (outputs->empty()) { + printf("forward returned no outputs\n"); return 1; } - EValue out = method->get_output(0); + const EValue& out = outputs->front(); if (out.isTensor()) { Tensor t = out.toTensor(); printf("Output: %u element(s):", static_cast(t.numel())); @@ -145,7 +85,7 @@ extern "C" int app_main(void) { } printf("Test_result: PASS\n"); - printf("\0x04"); // EOT to stop FVP simulation - fflush(stdout) ; + printf("\x04"); // EOT to stop FVP simulation + fflush(stdout); return 0; } diff --git a/src/arm_embedded_module.cpp b/src/arm_embedded_module.cpp new file mode 100644 index 00000000..96bebe78 --- /dev/null +++ b/src/arm_embedded_module.cpp @@ -0,0 +1,260 @@ +/* + * Copyright (c) Meta Platforms, Inc. and affiliates. + * All rights reserved. + * + * This source code is licensed under the BSD-style license found in the + * LICENSE file in the root directory of this source tree. + * + * Customization for embedded systems by Arm. + */ +#include "arm_embedded_module.hpp" + +#include + +using executorch::extension::BufferDataLoader; + +namespace arm +{ + namespace embedded + { + + EmbeddedModule::EmbeddedModule(const unsigned char *pte_data, + size_t pte_size, + std::unique_ptr data_loader, + std::unique_ptr memory_allocator, + std::unique_ptr temp_allocator) + : pte_data_(pte_data), pte_size_(pte_size), + data_loader_(std::move(data_loader)), + memory_allocator_(std::move(memory_allocator)), + temp_allocator_(std::move(temp_allocator)) + { + } + + ET_NODISCARD Error EmbeddedModule::load( + const Program::Verification verification) + { + if (!is_loaded()) + { + if (!data_loader_) + { + return Error::MemoryAllocationFailed; + } + Result res_program = Program::load(data_loader_.get(), verification); + if (!res_program.ok()) + { + return res_program.error(); + } + auto program = + std::make_unique>( + std::move(*res_program)); + program_ = std::shared_ptr( + program.release(), [](Program *pointer) + { delete pointer; }); + } + return Error::Ok; + } + + Result EmbeddedModule::num_methods() + { + ET_CHECK_OK_OR_RETURN_ERROR(load()); + return program_->num_methods(); + } + + Result> EmbeddedModule::method_names() + { + ET_CHECK_OK_OR_RETURN_ERROR(load()); + const auto method_count = program_->num_methods(); + std::unordered_set result; + result.reserve(method_count); + + for (auto index = 0; index < method_count; ++index) + { + result.emplace(program_->get_method_name(index).get()); + } + return result; + } + + Error EmbeddedModule::load_method( + const std::string &method_name, + HierarchicalAllocator *planned_memory, + EventTracer *event_tracer) + { + if (!is_method_loaded(method_name)) + { + ET_CHECK_OK_OR_RETURN_ERROR(load()); + + MethodHolder method_holder; + + if (!planned_memory) + { + auto method_metadata_result = program_->method_meta(method_name.c_str()); + if (!method_metadata_result.ok()) + { + return method_metadata_result.error(); + } + const auto method_metadata = std::move(*method_metadata_result); + const auto planned_buffers_count = + method_metadata.num_memory_planned_buffers(); + method_holder.planned_buffers.reserve(planned_buffers_count); + method_holder.planned_spans.reserve(planned_buffers_count); + + for (auto index = 0; index < planned_buffers_count; ++index) + { + const auto buffer_size = + static_cast(method_metadata.memory_planned_buffer_size(index).get()); + + uint8_t *buffer = reinterpret_cast( + memory_allocator_->allocate(buffer_size, 16UL)); + if (buffer == nullptr) + { + ET_LOG(Error, "Could not allocate memory for memory planned buffer size %d", (int)buffer_size); + return Error::MemoryAllocationFailed; + } + + method_holder.planned_buffers.push_back(buffer); + method_holder.planned_spans.push_back({method_holder.planned_buffers.back(), buffer_size}); + } + method_holder.planned_memory = + std::make_unique(Span( + method_holder.planned_spans.data(), + method_holder.planned_spans.size())); + planned_memory = method_holder.planned_memory.get(); + } + method_holder.memory_manager = std::make_unique( + memory_allocator_.get(), planned_memory, temp_allocator_.get()); + auto res_method = program_->load_method( + method_name.c_str(), + method_holder.memory_manager.get(), + event_tracer ? event_tracer : this->event_tracer()); + if (!res_method.ok()) + { + return res_method.error(); + } + method_holder.method = + std::make_unique>( + std::move(*res_method)); + methods_.emplace(method_name, std::move(method_holder)); + } + return Error::Ok; + } + + #if 0 + ET_NODISCARD Result EmbeddedModule::method( + const std::string &method_name) + { + ET_CHECK_OK_OR_RETURN_ERROR(load_method(method_name)); + return methods_[method_name].method.get(); + } + #endif + + Result EmbeddedModule::method_meta(const std::string &method_name) + { + ET_CHECK_OK_OR_RETURN_ERROR(load()); + return program_->method_meta(method_name.c_str()); + } + + Result> EmbeddedModule::execute( + const std::string &method_name, + const std::vector &input_values) + { + ET_CHECK_OK_OR_RETURN_ERROR(load_method(method_name)); + auto &method = methods_.at(method_name).method; + for (auto index = 0; index < input_values.size(); ++index) + { + ET_CHECK_OK_OR_RETURN_ERROR(method->set_input(input_values[index], index)); + } + ET_CHECK_OK_OR_RETURN_ERROR(method->execute()); + const auto outputs_size = method->outputs_size(); + std::vector outputs(outputs_size); + ET_CHECK_OK_OR_RETURN_ERROR( + method->get_outputs(outputs.data(), outputs_size)); + + return outputs; + } + + Error EmbeddedModule::set_input( + const std::string &method_name, + const EValue &input_value, + size_t input_index) + { + ET_CHECK_OK_OR_RETURN_ERROR(load_method(method_name)); + auto &method = methods_.at(method_name).method; + return method->set_input(input_value, input_index); + } + + Error EmbeddedModule::set_inputs( + const std::string &method_name, + const std::vector &input_values) + { + ET_CHECK_OK_OR_RETURN_ERROR(load_method(method_name)); + auto &method = methods_.at(method_name).method; + return method->set_inputs(executorch::aten::ArrayRef( + input_values.data(), input_values.size())); + } + + Error EmbeddedModule::set_output( + const std::string &method_name, + EValue output_value, + size_t output_index) + { + ET_CHECK_OK_OR_RETURN_ERROR(load_method(method_name)); + auto &method = methods_.at(method_name).method; + ET_CHECK_OR_RETURN_ERROR( + output_value.isTensor(), + InvalidArgument, + "output type: %zu is not tensor", + (size_t)output_value.tag); + const auto &output_tensor = output_value.toTensor(); + return method->set_output_data_ptr( + output_tensor.mutable_data_ptr(), output_tensor.nbytes(), output_index); + } + + Error EmbeddedModule::set_outputs( + const std::string &method_name, + const std::vector &output_values) + { + ET_CHECK_OK_OR_RETURN_ERROR(load_method(method_name)); + auto &method = methods_.at(method_name).method; + const auto outputs_size = method->outputs_size(); + ET_CHECK_OR_RETURN_ERROR( + output_values.size() == outputs_size, + InvalidArgument, + "output size: %zu is not equal to method output size: %zu", + output_values.size(), + outputs_size); + for (auto index = 0; index < outputs_size; ++index) + { + ET_CHECK_OK_OR_RETURN_ERROR( + set_output(method_name, output_values[index], index)); + } + return Error::Ok; + } + + Result> EmbeddedModule::get_outputs( + const std::string &method_name) + { + ET_CHECK_OK_OR_RETURN_ERROR(load_method(method_name)); + auto &method = methods_.at(method_name).method; + const auto outputs_size = method->outputs_size(); + std::vector outputs(outputs_size); + ET_CHECK_OK_OR_RETURN_ERROR( + method->get_outputs(outputs.data(), outputs_size)); + return outputs; + } + + Result EmbeddedModule::get_output( + const std::string &method_name, + size_t output_index) + { + ET_CHECK_OK_OR_RETURN_ERROR(load_method(method_name)); + auto &method = methods_.at(method_name).method; + ET_CHECK_OR_RETURN_ERROR( + output_index < method->outputs_size(), + InvalidArgument, + "output index: %zu is out of range", + output_index); + return method->get_output(output_index); + } + + } // namespace embedded +} // namespace arm diff --git a/src/arm_embedded_module.hpp b/src/arm_embedded_module.hpp new file mode 100644 index 00000000..5ba324bc --- /dev/null +++ b/src/arm_embedded_module.hpp @@ -0,0 +1,553 @@ +/* + * Copyright (c) Meta Platforms, Inc. and affiliates. + * All rights reserved. + * + * This source code is licensed under the BSD-style license found in the + * LICENSE file in the root directory of this source tree. + * + * Customization for embedded systems by Arm. + */ +#pragma once + +#include +#include + +#include +#include +#include +#include +#include + +using namespace ::executorch::runtime; + +namespace arm +{ + namespace embedded + { + + /** + * A facade class for loading programs and executing methods within them. + */ + class EmbeddedModule + { + public: + /** + * Constructs an instance with the provided PTE data and memory allocators. + * + * @param[in] pte_data Pointer to the ExecuTorch program data to load. + * @param[in] pte_size Size of the ExecuTorch program data to load. + * @param[in] memory_allocator A MemoryAllocator used for memory planning. + * @param[in] temp_allocator A MemoryAllocator to use when allocating + * temporary data during kernel or delegate execution. + */ + explicit EmbeddedModule( + const unsigned char *pte_data, + size_t pte_size, + std::unique_ptr data_loader = nullptr, + std::unique_ptr memory_allocator = nullptr, + std::unique_ptr temp_allocator = nullptr); + + /** + * Loads the program if needed. + * + * @param[in] verification The type of verification to do before returning + * success. + * + * @returns An Error to indicate success or failure of the loading process. + */ + ET_NODISCARD Error load( + const Program::Verification verification = + Program::Verification::Minimal); + + /** + * Checks if the program is loaded. + * + * @returns true if the program is loaded, false otherwise. + */ + inline bool is_loaded() const + { + return program_ != nullptr; + } + + /** + * Get the program. The data loader used by the program is guaranteed to be + * valid for the lifetime of the program. + * + * @returns Shared pointer to the program or nullptr if it's not yet loaded. + */ + inline std::shared_ptr program() const + { + return program_; + } + + /** + * Get the number of methods available in the loaded program. + * + * @returns A Result object containing either the number of methods available + * or an error to indicate failure. + */ + Result num_methods(); + + /** + * Get a list of method names available in the loaded program. + * Loads the program and method if needed. + * + * @returns A set of strings containing the names of the methods, or an error + * if the program or method failed to load. + */ + Result> method_names(); + + /** + * Load a specific method from the program and set up memory management if + * needed. The loaded method is cached to reuse the next time it's executed. + * + * @param[in] method_name The name of the method to load. + * @param[in] planned_memory The memory-planned buffers to use for mutable + * tensor data when executing a method. + * @param[in] event_tracer Per-method event tracer to profile/trace methods + * individually. When not given, the event tracer passed to the + * EmbeddedModule constructor is used. Otherwise, this per-method event tracer + * takes precedence. + * + * @returns An Error to indicate success or failure. + */ + ET_NODISCARD + Error load_method( + const std::string &method_name, + HierarchicalAllocator *planned_memory = nullptr, + EventTracer *event_tracer = nullptr); + + #if 0 + ET_DEPRECATED ET_NODISCARD Error inline load_method( + const std::string &method_name, + EventTracer *event_tracer) + { + return load_method(method_name, nullptr, event_tracer); + } + #endif + + /** + * Unload a specific method from the program. + * + * @param[in] method_name The name of the method to unload. + * + * @returns True if the method is unloaded, false if no-op. + */ + inline bool unload_method(const std::string &method_name) + { + return methods_.erase(method_name); + } + + #if 0 + /** + * DEPRECATED: EmbeddedModule manages each Method exclusively. + * + * Get a method by it's name. Not recommended to use this method directly as + * an end user. It's exposed to allow for composability of module in apis that + * operate on method. + * + * @param[in] method_name The name of the method to get. + * + * @returns A Result object containing either a pointer to the requested + * method or an error to indicate failure. + */ + ET_DEPRECATED ET_NODISCARD Result method( + const std::string &method_name); + #endif + + /** + * Checks if a specific method is loaded. + * + * @param[in] method_name The name of the method to check. + * + * @returns true if the method specified by method_name is loaded, false + * otherwise. + */ + inline bool is_method_loaded(const std::string &method_name) const + { + return methods_.count(method_name); + } + + /** + * Get a method metadata struct by method name. + * Loads the program if needed. + * + * @param[in] method_name The name of the method to get the metadata for. + * + * @returns A method metadata, or an error if the program or method failed to + * load. + */ + Result method_meta(const std::string &method_name); + + /** + * Execute a specific method with the given input values and retrieve the + * output values. Loads the program and method before executing if needed. + * + * @param[in] method_name The name of the method to execute. + * @param[in] input_values A vector of input values to be passed to the + * method. + * + * @returns A Result object containing either a vector of output values + * from the method or an error to indicate failure. + */ + ET_NODISCARD Result> execute( + const std::string &method_name, + const std::vector &input_values); + + /** + * Execute a specific method with a single input value. + * Loads the program and method before executing if needed. + * + * @param[in] method_name The name of the method to execute. + * @param[in] input_value A value to be passed to the method. + * + * @returns A Result object containing either a vector of output values + * from the method or an error to indicate failure. + */ + ET_NODISCARD inline Result> execute( + const std::string &method_name, + const EValue &input_value) + { + return execute(method_name, std::vector{input_value}); + } + + /** + * Execute a specific method without any input values. + * Loads the program and method before executing if needed. + * + * @param[in] method_name The name of the method to execute. + * + * @returns A Result object containing either a vector of output values + * from the method or an error to indicate failure. + */ + ET_NODISCARD inline Result> execute( + const std::string &method_name) + { + return execute(method_name, std::vector{}); + } + + /** + * Retrieve the output value of a specific method with the given input values. + * Loads the program and method before execution if needed. + * + * @param[in] method_name The name of the method to execute. + * @param[in] input_values A vector of input values to be passed to the + * method. + * + * @returns A Result object containing either the first output value from the + * method or an error to indicate failure. + */ + ET_NODISCARD inline Result get( + const std::string &method_name, + const std::vector &input_values) + { + auto execute_result = execute(method_name, input_values); + if (!execute_result.ok()) + { + return execute_result.error(); + } + auto result = std::move(*execute_result); + if (result.empty()) + { + return Error::InvalidArgument; + } + return result[0]; + } + + /** + * Retrieve the output value of a specific method with a single input value. + * Loads the program and method before execution if needed. + * + * @param[in] method_name The name of the method to execute. + * @param[in] input_value A value to be passed to the method. + * + * @returns A Result object containing either the first output value from the + * method or an error to indicate failure. + */ + ET_NODISCARD inline Result get( + const std::string &method_name, + const EValue &input_value) + { + return get(method_name, std::vector{input_value}); + } + + /** + * Retrieve the output value of a specific method without any input values. + * Loads the program and method before execution if needed. + * + * @param[in] method_name The name of the method to execute. + * + * @returns A Result object containing either the first output value from the + * method or an error to indicate failure. + */ + ET_NODISCARD inline Result get( + const std::string &method_name) + { + return get(method_name, std::vector{}); + } + + /** + * Execute the 'forward' method with the given input values and retrieve the + * output values. Loads the program and method before executing if needed. + * + * @param[in] input_values A vector of input values for the 'forward' method. + * + * @returns A Result object containing either a vector of output values + * from the 'forward' method or an error to indicate failure. + */ + ET_NODISCARD inline Result> forward( + const std::vector &input_values) + { + return execute("forward", input_values); + }; + + /** + * Execute the 'forward' method with a single value. + * Loads the program and method before executing if needed. + * + * @param[in] input_value A value for the 'forward' method. + * + * @returns A Result object containing either a vector of output values + * from the 'forward' method or an error to indicate failure. + */ + ET_NODISCARD inline Result> forward( + const EValue &input_value) + { + return forward(std::vector{input_value}); + } + + /** + * Execute the 'forward' method without any input values. + * Loads the program and method before executing if needed. + * + * @returns A Result object containing either a vector of output values + * from the method or an error to indicate failure. + */ + ET_NODISCARD inline Result> forward() + { + return forward(std::vector{}); + } + + /** + * Sets a single input value for a specific method. + * + * @param[in] method_name The name of the method. + * @param[in] input_value The EValue to set as the method input. + * @param[in] input_index Zero-based index of the input to set. + * + * @returns An Error to indicate success or failure. + */ + ET_NODISCARD + Error set_input( + const std::string &method_name, + const EValue &input_value, + size_t input_index); + + /** + * Sets a single input value for the "forward" method. + * + * @param[in] input_value The EValue to set as the method input. + * @param[in] input_index Zero-based index of the input to set. + * + * @returns An Error to indicate success or failure. + */ + ET_NODISCARD + inline Error set_input( + const EValue &input_value, + size_t input_index) + { + return set_input("forward", input_value, input_index); + } + + /** + * Sets all input values for a specific method. + * + * @param[in] method_name The name of the method. + * @param[in] input_values A vector of EValues to set as the method inputs. + * + * @returns An Error to indicate success or failure. + */ + ET_NODISCARD + Error set_inputs( + const std::string &method_name, + const std::vector &input_values); + + /** + * Sets all input values for the "forward" method. + * + * @param[in] input_values A vector of EValues to set as the method inputs. + * + * @returns An Error to indicate success or failure. + */ + ET_NODISCARD + inline Error set_inputs( + const std::vector &input_values) + { + return set_inputs("forward", input_values); + } + + /** + * Sets the output tensor for a specific method. + * + * @param[in] method_name The name of the method. + * @param[in] output_value The EValue containing the Tensor to set as the + * method output. + * @param[in] output_index Zero-based index of the output to set. + * + * @returns An Error to indicate success or failure. + * + * @note Only Tensor outputs are currently supported for setting. + */ + ET_NODISCARD + Error set_output( + const std::string &method_name, + EValue output_value, + size_t output_index = 0); + + /** + * Sets the output tensor for the "forward" method. + * + * @param[in] output_value The EValue containing the Tensor to set as the + * method output. + * @param[in] output_index Zero-based index of the output to set. + * + * @returns An Error to indicate success or failure. + * + * @note Only Tensor outputs are currently supported for setting. + */ + ET_NODISCARD + inline Error set_output( + EValue output_value, + size_t output_index = 0) + { + return set_output("forward", std::move(output_value), output_index); + } + + /** + * Sets all output tensors for a specific method. + * + * Loads the program and method if needed, and for each output uses + * the provided tensor's data buffer as the method's output buffer. + * + * @param[in] method_name The name of the method. + * @param[in] output_values A vector of EValues to set as the method outputs. + * + * @returns An Error to indicate success or failure. + * + * @note Only Tensor outputs are currently supported for setting. + * @note Will fail for outputs that are memory-planned or constants. + */ + ET_NODISCARD + Error set_outputs( + const std::string &method_name, + const std::vector &output_values); + + /** + * Sets all output tensors for the "forward" method. + * + * @param[in] output_values A vector of EValues to set as the method outputs. + * + * @returns An Error to indicate success or failure. + * + * @note Only Tensor outputs are currently supported for setting. + * @note Will fail for outputs that are memory-planned or constants. + */ + ET_NODISCARD + inline Error set_outputs( + const std::vector &output_values) + { + return set_outputs("forward", output_values); + } + + /** + * Retrieve all current output values of a specific method without executing + * it. Loads the program and method before retrieval if needed. + * + * @param[in] method_name The name of the method. + * + * @returns A Result containing the vector of output values, or an error. + */ + ET_NODISCARD + Result> get_outputs( + const std::string &method_name); + + /** + * Retrieve all current output values of the "forward" method without + * executing it. Loads the program and method before retrieval if needed. + * + * @returns A Result containing the vector of output values, or an error. + */ + ET_NODISCARD + inline Result> get_outputs() + { + return get_outputs("forward"); + } + + /** + * Retrieve a single current output value of a specific method without + * executing it. Loads the program and method before retrieval if needed. + * + * @param[in] method_name The name of the method. + * @param[in] output_index Zero-based index of the output to retrieve. + * + * @returns A Result containing the requested output value, or an error. + */ + ET_NODISCARD + Result get_output( + const std::string &method_name, + size_t output_index = 0); + + /** + * Retrieve a single current output value of the "forward" method without + * executing it. Loads the program and method before retrieval if needed. + * + * @param[in] output_index Zero-based index of the output to retrieve. + * + * @returns A Result containing the requested output value, or an error. + */ + ET_NODISCARD + inline Result get_output(size_t output_index = 0) + { + return get_output("forward", output_index); + } + + /** + * Retrieves the EventTracer instance being used by the EmbeddedModule. + * EventTracer is used for tracking and logging events during the execution + * of methods. + * + * @returns A pointer to the EventTracer instance. Returns nullptr if no + * EventTracer is set. + */ + inline EventTracer *event_tracer() const + { + return event_tracer_.get(); + } + + private: + struct MethodHolder + { + std::vector planned_buffers; + std::vector> planned_spans; + std::unique_ptr planned_memory; + std::unique_ptr memory_manager; + std::unique_ptr method; + }; + + std::shared_ptr program_; + std::unique_ptr data_loader_; + std::unique_ptr memory_allocator_; + std::unique_ptr temp_allocator_; + // std::unique_ptr merged_data_map_; + + std::unique_ptr event_tracer_; + + const unsigned char *pte_data_; + size_t pte_size_; + + protected: + std::unordered_map methods_; + }; + + } // namespace embedded +} // namespace arm