From 3378e350b36cc04f19266e28b24b8bf2f7ace52f Mon Sep 17 00:00:00 2001 From: Claude Date: Mon, 31 Aug 2026 07:56:36 +0000 Subject: [PATCH] review follow-up: scalar U64x8 IMM guard; avx512 verification measured, not claimed Codex P2 pair on the record PR, both accepted: - src/simd_scalar.rs: U64x8::ternlog was missing the inline const IMM guard the record marked complete (U32x16 had it) - ternlog::<256> compiled and silently truncated. Guard added, doc paragraph aligned with the every-backend wording. - .claude/blackboard.md: the claim that the avx512 doc examples execute in the doc-test run is retired (default v3 facade resolves the examples to the avx2 types - default-facade coverage, not backend verification). Replaced with a measurement: this host carries avx512f and all five w1a9 facade tests pass under CARGO_BUILD_RUSTFLAGS=-Ctarget-cpu=x86-64-v4 - hardware-executed avx512 runtime verification, recorded as such. Co-Authored-By: Claude Claude-Session: https://claude.ai/code/session_01KCGhDYoQBXs3poaR7sFuqp --- .claude/blackboard.md | 17 +++++++++++++++-- src/simd_scalar.rs | 8 +++++--- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/.claude/blackboard.md b/.claude/blackboard.md index af774257..7490e546 100644 --- a/.claude/blackboard.md +++ b/.claude/blackboard.md @@ -16,8 +16,21 @@ named immediates live on the always-compiled facade as `crate::simd::ternlog` (their first home in the scalar backend was compiled out on x86 — three bots caught it independently), and every portable arm carries the avx512-equivalent compile-time IMM domain guard. Doc examples -on all twelve method sites; the avx512 ones execute in this environment's -doc-test run. Declined finding, reasons on the PR thread: extending the +on all twelve method sites. + +> **⊘ Correction (2026-08-31, codex P2 pair on the record PR — both +> accepted):** (a) the sentence that stood here claimed the avx512 doc +> examples "execute in this environment's doc-test run" — under the +> default v3 config the examples import the FACADE types, so what runs is +> default-facade coverage, not the avx512 backend; the claim is retired. +> The honest replacement is a MEASUREMENT: this host carries avx512f +> (cpuinfo), and all five w1a9 facade tests pass under +> `CARGO_BUILD_RUSTFLAGS='-Ctarget-cpu=x86-64-v4'` — that run IS the +> avx512 backend's runtime verification, hardware-executed, not inferred. +> (b) the scalar U64x8 ternlog was missing the IMM const guard the entry +> recorded as complete (U32x16 had it; U64x8 did not — `ternlog::<256>` +> compiled and silently truncated). Guard added with the same message as +> every other arm. Declined finding, reasons on the PR thread: extending the pre-existing off-by-default nightly arm is REQUIRED (not extending it is the E0599 hole), and the stable-only rule governs the default build graph, which is untouched. Loose end, deliberate: whole-crate wasm compile-check diff --git a/src/simd_scalar.rs b/src/simd_scalar.rs index a63810b9..6482b585 100644 --- a/src/simd_scalar.rs +++ b/src/simd_scalar.rs @@ -2071,9 +2071,10 @@ impl U64x8 { /// Per bit position: `index = (self << 2) | (b << 1) | c`, result bit = /// `(IMM >> index) & 1` — Intel's VPTERNLOG convention, matched exactly by /// every backend. `IMM` is `i32` to mirror the intrinsic's signature; only - /// `0..=255` is legal, enforced at compile time on the AVX-512 backend by - /// the intrinsic's own static assert. Within that domain: total function, - /// no lane interaction. + /// `0..=255` is legal, enforced at compile time on EVERY backend (here by + /// an inline const assert, on AVX-512 by the intrinsic's own static + /// assert). Named immediates live in `crate::simd::ternlog`. Within that + /// domain: total function, no lane interaction. /// /// # Examples /// @@ -2085,6 +2086,7 @@ impl U64x8 { /// ``` #[inline(always)] pub fn ternlog(self, b: Self, c: Self) -> Self { + const { assert!(IMM >= 0 && IMM <= 255, "ternlog IMM is an 8-bit truth table") } let (a, z) = (self, Self::splat(0)); let mut r = z; if IMM & 0x01 != 0 {